Issued Patents 2016
Showing 26–50 of 175 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9496282 | Structure and method to reduce crystal defects in epitaxial fin merge using nitride deposition | Thomas N. Adam, Kangguo Cheng, Ali Khakifirooz, Raghavasimhan Sreenivasan | 2016-11-15 |
| 9496400 | FinFET with stacked faceted S/D epitaxy for improved contact resistance | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2016-11-15 |
| 9496343 | Secondary use of aspect ratio trapping holes as eDRAM structure | Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz | 2016-11-15 |
| 9496186 | Uniform height tall fins with varying silicon germanium concentrations | Stephen W. Bedell, Bruce B. Doris, Keith E. Fogel | 2016-11-15 |
| 9496373 | Damage-resistant fin structures and FinFET CMOS | Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz | 2016-11-15 |
| 9496401 | III-V device structure with multiple threshold voltage | Kangguo Cheng, Keith E. Fogel, Pouya Hashemi | 2016-11-15 |
| 9496260 | Tall strained high percentage silicon germanium fins for CMOS | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2016-11-15 |
| 9496263 | Stacked strained and strain-relaxed hexagonal nanowires | Takashi Ando, Pouya Hashemi, John A. Ott | 2016-11-15 |
| 9490161 | Channel SiGe devices with multiple threshold voltages on hybrid oriented substrates, and methods of manufacturing same | Bruce B. Doris, Lisa F. Edge, Pouya Hashemi | 2016-11-08 |
| 9484266 | Complementary heterogeneous MOSFET using global SiGe substrate and hard-mask memorized germanium dilution for nFET | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2016-11-01 |
| 9484412 | Strained silicon—germanium integrated circuit with inversion capacitance enhancement and method to fabricate same | Takashi Ando, Pouya Hashemi, Pranita Kerber | 2016-11-01 |
| 9484439 | III-V fin on insulator | Kangguo Cheng, Hemanth Jagannathan | 2016-11-01 |
| 9484405 | Stacked nanowire devices formed using lateral aspect ratio trapping | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2016-11-01 |
| 9478468 | Dual metal contact scheme for CMOS devices | Kangguo Cheng, Ali Khakifirooz, Tenko Yamashita | 2016-10-25 |
| 9478642 | Semiconductor junction formation | Pouya Hashemi, Shogo Mochizuki, Dominic J. Schepis | 2016-10-25 |
| 9472470 | Methods of forming FinFET with wide unmerged source drain EPI | Kangguo Cheng, Ali Khakifirooz, Dominic J. Schepis | 2016-10-18 |
| 9472471 | Hybrid orientation vertically stacked III-V and Ge gate-all-around CMOS | Karthik Balakrishnan, Pouya Hashemi, Sanghoon Lee | 2016-10-18 |
| 9472671 | Method and structure for forming dually strained silicon | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2016-10-18 |
| 9472555 | Nanosheet CMOS with hybrid orientation | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2016-10-18 |
| 9472573 | Silicon-germanium fin formation | Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz | 2016-10-18 |
| 9472575 | Formation of strained fins in a finFET device | Pouya Hashemi, Ali Khakifirooz | 2016-10-18 |
| 9472628 | Heterogeneous source drain region and extension region | Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz | 2016-10-18 |
| 9472460 | Uniform depth fin trench formation | Kangguo Cheng, Ali Khakifirooz, Dominic J. Schepis, Pouya Hashemi | 2016-10-18 |
| 9472576 | Structure and method to reduce crystal defects in epitaxial fin merge using nitride deposition | Thomas N. Adam, Kangguo Cheng, Ali Khakifirooz, Raghavasimhan Sreenivasan | 2016-10-18 |
| 9466702 | Semiconductor device including multiple fin heights | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2016-10-11 |