Issued Patents 2016
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9520496 | Charge carrier transport facilitated by strain | Anirban Basu | 2016-12-13 |
| 9502562 | Fin field effect transistor including self-aligned raised active regions | Anirban Basu, Amlan Majumdar | 2016-11-22 |
| 9484463 | Fabrication process for mitigating external resistance of a multigate device | Anirban Basu, Amlan Majumdar | 2016-11-01 |
| 9472667 | III-V MOSFET with strained channel and semi-insulating bottom barrier | Anirban Basu, Amlan Majumdar | 2016-10-18 |
| 9472658 | III-V nanowire FET with compositionally-graded channel and wide-bandgap core | Anirban Basu, Amlan Majumdar, Jeffrey W. Sleight | 2016-10-18 |
| 9449820 | Epitaxial growth techniques for reducing nanowire dimension and pitch | Michael A. Guillorn, Isaac Lauer, Jeffrey W. Sleight | 2016-09-20 |
| 9443102 | Protecting content displayed on a mobile device | Lior Horesh, Raya Horesh, Marco Pistoia | 2016-09-13 |
| 9431494 | Low interfacial defect field effect transistor | Anirban Basu, Amlan Majumdar | 2016-08-30 |
| 9431520 | Graphene nanoribbons and carbon nanotubes fabricated from SiC fins or nanowire templates | Christos D. Dimitrakopoulos, Alfred Grill | 2016-08-30 |
| 9417714 | RFID-based input device | — | 2016-08-16 |
| 9405346 | Managing access to data on a client device during low-power state | Gregory J. Boss, James R. Kozloski, Clifford A. Pickover, Anne R. Sand | 2016-08-02 |
| 9406530 | Techniques for fabricating reduced-line-edge-roughness trenches for aspect ratio trapping | Katherine L. Saenger, Kuen-Ting Shiu | 2016-08-02 |
| 9397195 | Graphene nanoribbons and carbon nanotubes fabricated from SiC fins or nanowire templates | Christos D. Dimitrakopoulos, Alfred Grill | 2016-07-19 |
| 9390980 | III-V compound and germanium compound nanowire suspension with germanium-containing release layer | Isaac Lauer, Alexander Reznicek, Jeffrey W. Sleight | 2016-07-12 |
| 9368574 | Nanowire field effect transistor with inner and outer gates | Anirban Basu, Amlan Majumdar, Jeffrey W. Sleight | 2016-06-14 |
| 9349591 | Crystal formation on non-lattice matched substrates | Cheng-Wei Cheng, Devendra K. Sadana, Brent A. Wacaser | 2016-05-24 |
| 9343142 | Nanowire floating gate transistor | Sarunya Bangsaruntip, Amlan Majumdar, Jeffrey W. Sleight | 2016-05-17 |
| 9337264 | Process for forming a surrounding gate for a nanowire using a sacrificial patternable dielectric | Sarunya Bangsaruntip, Michael A. Guillorn | 2016-05-10 |
| 9329033 | Method for estimating and correcting misregistration target inaccuracy | Eran Amit, Dana Klein, Amir Widmann, Nimrod Shuall, Amnon Manassen +1 more | 2016-05-03 |
| 9318561 | Device isolation for III-V substrates | Anirban Basu | 2016-04-19 |
| 9287360 | III-V nanowire FET with compositionally-graded channel and wide-bandgap core | Anirban Basu, Amlan Majumdar, Jeffrey W. Sleight | 2016-03-15 |
| 9263260 | Nanowire field effect transistor with inner and outer gates | Anirban Basu, Amlan Majumdar, Jeffrey W. Sleight | 2016-02-16 |
| 9264182 | Iterative receiver loop | Mor Miller, Amit Steinberg, Daniel Wajcer, Dan Peleg | 2016-02-16 |
| 9263292 | Processing for overcoming extreme topography | Steven A. Cordes, Sherif A. Goma, Joanna Rosner, Jeannine M. Trewhella | 2016-02-16 |