Issued Patents All Time
Showing 51–72 of 72 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7345355 | Complementary junction-narrowing implants for ultra-shallow junctions | Stephanie W. Butler | 2008-03-18 |
| 7344985 | Nickel alloy silicide including indium and a method of manufacture therefor | Peijun Chen, Duofeng Yue, Sue Crank, Thomas D. Bonifield, Homi Mogul | 2008-03-18 |
| 7344929 | Method for manufacturing an integrated circuit using a capping layer having a degree of reflectivity | Manoj Mehrotra | 2008-03-18 |
| 7306995 | Reduced hydrogen sidewall spacer oxide | Haowen Bu, Clinton L. Montgomery | 2007-12-11 |
| 7297605 | Source/drain extension implant process for use with short time anneals | Gordon P. Pollack | 2007-11-20 |
| 7247535 | Source/drain extensions having highly activated and extremely abrupt junctions | — | 2007-07-24 |
| 7211516 | Nickel silicide including indium and a method of manufacture therefor | Peijun Chen, Duofeng Yue, Sue Crank, Thomas D. Bonifield, Homi Mogul | 2007-05-01 |
| 7173296 | Reduced hydrogen sidewall spacer oxide | Haowen Bu, Clinton L. Montgomery | 2007-02-06 |
| 7163878 | Ultra-shallow arsenic junction formation in silicon germanium | Puneet Kohli, Mark S. Rodder, Rick L. Wise | 2007-01-16 |
| 7118980 | Solid phase epitaxy recrystallization by laser annealing | — | 2006-10-10 |
| 7026218 | Use of indium to define work function of p-type doped polysilicon | Antonio Luis Pacheco Rotondaro, James Joseph Chambers | 2006-04-11 |
| 6847089 | Gate edge diode leakage reduction | Srinivasan Chakravarthi, Suresh Potla, Gordon P. Pollack | 2005-01-25 |
| 6812073 | Source drain and extension dopant concentration | Haowen Bu, Wayne Bather, Stephanie W. Butler | 2004-11-02 |
| 6808997 | Complementary junction-narrowing implants for ultra-shallow junctions | Stephanie W. Butler | 2004-10-26 |
| 6803611 | Use of indium to define work function of p-type doped polysilicon | Antonio Luis Pacheco Rotondaro, James Joseph Chambers | 2004-10-12 |
| 6797593 | Methods and apparatus for improved mosfet drain extension activation | Srinivasan Chakravarthi, Xin Zhang | 2004-09-28 |
| 6743705 | Transistor with improved source/drain extension dopant concentration | Manoj Mehrotra, Haowen Bu | 2004-06-01 |
| 6737354 | Method of CMOS source/drain extension with the PMOS implant spaced by poly oxide and cap oxide from the gates | Donald Miles, Douglas T. Grider, Chidi Chidambaram | 2004-05-18 |
| 6713360 | System for reducing segregation and diffusion of halo implants into highly doped regions | Kaiping Liu, Zhiqiang Wu | 2004-03-30 |
| 6709938 | Source/drain extension fabrication process with direct implantation | Donald Miles, Douglas T. Grider, P.R. Chidambaram | 2004-03-23 |
| 6677201 | Method of fabricating thermal CVD oxynitride and BTBAS nitride sidewall spacer for metal oxide semiconductor transistors | Haowen Bu | 2004-01-13 |
| 6482688 | Utilizing amorphorization of polycrystalline structures to achieve T-shaped MOSFET gate | Chimin Hu, Reima Laaksonen, Manoj Mehrotra | 2002-11-19 |