Issued Patents All Time
Showing 76–100 of 107 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9553043 | Interconnect structure having smaller transition layer via | Lee-Chung Lu, Yuan-Te Hou, Fang-Yu Fan, Yu-Hsiang Kao, Dian-Hau Chen +2 more | 2017-01-24 |
| 9477803 | Method of generating techfile having reduced corner variation value | Chung-Hsing Wang, King-Ho Tam, Yen-Pin Chen, Chung-Kai Lin, Chih-Hsiang Yao | 2016-10-25 |
| 9394320 | Method for fixing metal onto surface of substrate | Lai-Kwan Chau, Yen-Ta Tseng, Chin-Wei Wu, Chao-Wen Chen | 2016-07-19 |
| 9380709 | Method of cutting conductive patterns | Chin-Hsiung Hsu, Huang-Yu Chen, Tsong-Hua Ou | 2016-06-28 |
| 9317650 | Double patterning technology (DPT) layout routing | Huang-Yu Chen, Fang-Yu Fan, Yuan-Te Hou, Chung-Hsing Wang, Yi-Kan Cheng | 2016-04-19 |
| 9262570 | Layout boundary method | Chin-Hsiung Hsu, Ho Che Yu | 2016-02-16 |
| 9223924 | Method and system for multi-patterning layout decomposition | Chin-Hsiung Hsu, Chin-Chang Hsu, Yuan-Te Hou, Godina Ho, Wen-Ju Yang | 2015-12-29 |
| 9165105 | Rule checking for confining waveform induced constraint variation in static timing analysis | Meng-Kai Hsu | 2015-10-20 |
| 9096620 | Mercaptoalkylsilatrane derivative having protecting group and method of manufacturing the same | Lai-Kwan Chau, Chao-Wen Chen, Yen-Ta Tseng | 2015-08-04 |
| 9087170 | Cell layout design and method | Chin-Hsiung Hsu, Yuan-Te Hou, Li-Chun Tien, Hui-Zhong Zhuang, Fang-Yu Fan +1 more | 2015-07-21 |
| 9064081 | Generating database for cells routable in pin layer | Meng-Kai Hsu, Chi-Yeh Yu, Yuan-Te Hou | 2015-06-23 |
| 9035361 | Electromigration resistant standard cell device | Lee-Chung Lu, Yuan-Te Hou, Shen-Feng Chen, Meng-Fu You | 2015-05-19 |
| 9026953 | Compression method and system for use with multi-patterning | Huang-Yu Chen, Chin-Hsiung Hsu, Chung-Hsing Wang | 2015-05-05 |
| 8977991 | Method and system for replacing a pattern in a layout | Huang-Yu Chen, Yuan-Te Hou, Chung-Min Fu, Chung-Hsing Wang, Yi-Kan Cheng | 2015-03-10 |
| 8972919 | Static timing analysis method and system considering capacitive coupling and double patterning mask misalignment | Yi-Kan Cheng | 2015-03-03 |
| 8972910 | Routing method | Yuan-Te Hou, Chin-Hsiung Hsu, Meng-Kai Hsu | 2015-03-03 |
| 8959466 | Systems and methods for designing layouts for semiconductor device fabrication | Chin-Hsiung Hsu, Yuan-Te Hou | 2015-02-17 |
| 8949758 | Hybrid design rule for double patterning | Cheng-I Huang, Wen-Chun Huang | 2015-02-03 |
| 8914755 | Layout re-decomposition for multiple patterning layouts | Chin-Hsiung Hsu, Huang-Yu Chen, Yuan-Te Hou, Yen-Pin Chen, Chung-Hsing Wang | 2014-12-16 |
| 8875067 | Reusable cut mask for multiple layers | Chin-Hsiung Hsu, Huang-Yu Chen, Yuan-Te Hou | 2014-10-28 |
| 8856696 | Integrated circuit layout modification | Yuan-Te Hou, Yi-Kan Cheng | 2014-10-07 |
| 8850368 | Double patterning technology (DPT) layout routing | Huang-Yu Chen, Fang-Yu Fan, Yuan-Te Hou, Chung-Hsing Wang, Yi-Kan Cheng | 2014-09-30 |
| 8786094 | Semiconductor devices and methods of manufacture thereof | Chung-Min Fu, Dian-Hau Chen | 2014-07-22 |
| 8726208 | DFM improvement utility with unified interface | Zhe-Wei Jiang, Chung-Min Fu | 2014-05-13 |
| 8612912 | Static timing analysis method and system considering capacitive coupling and double patterning mask misalignment | Yi-Kan Cheng | 2013-12-17 |