Issued Patents All Time
Showing 26–50 of 79 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10782318 | Test probing structure | Ching-Fang Chen, Sandeep Kumar Goel, Chung-Sheng Yuan, Chao-Yang Yeh, Chin-Chou Liu +2 more | 2020-09-22 |
| 10741537 | Semiconductor structure and manufacturing method thereof | Hsiang-Tai Lu, Shuo-Mao Chen, Feng-Cheng Hsu, Chao-Hsiang Yang, Shin-Puu Jeng +4 more | 2020-08-11 |
| 10725090 | Test circuit and method | Ching-Nen Peng, Hung-Chih Lin, Sen-Kuei Hsu, Chuan-Ching Wang, Hao Chen | 2020-07-28 |
| 10718790 | Devices for high-density probing techniques and method of implementing the same | Ching-Nen Peng, Hung-Chih Lin, Wei-Hsun Lin, Sen-Kuei Hsu, De-Jian Liu | 2020-07-21 |
| 10698026 | Testing holders for chip unit and die package | Kuo-Chuan Liu, Ching-Nen Peng, Hung-Chih Lin, Hao Chen | 2020-06-30 |
| 10652987 | Three dimensional integrated circuit electrostatic discharge protection and prevention test interface | Ching-Nen Peng, Hung-Chih Lin, Hao-Chiang Cheng | 2020-05-12 |
| 10641819 | Alignment testing for tiered semiconductor structure | Ching-Nen Peng, Hung-Chih Lin, Hao Chen, Mincent Lee | 2020-05-05 |
| 10634717 | Testing apparatus and testing method | Tang-Jung Chiu, Hung-Chih Lin | 2020-04-28 |
| 10274518 | Devices for high-density probing techniques and method of implementing the same | Ching-Nen Peng, Hung-Chih Lin, Wei-Hsun Lin, Sen-Kuei Hsu, De-Jian Liu | 2019-04-30 |
| 10267847 | Probe head structure of probe card and testing method | Ming-Cheng Hsu | 2019-04-23 |
| 10073135 | Alignment testing for tiered semiconductor structure | Ching-Nen Peng, Hung-Chih Lin, Hao Chen, Mincent Lee | 2018-09-11 |
| 10067181 | Testing holders for chip unit and die package | Kuo-Chuan Liu, Ching-Nen Peng, Hung-Chih Lin, Hao Chen | 2018-09-04 |
| 10002829 | Semiconductor device and manufacturing method thereof | Hao Chen, Chen-Hsiang Hsu, Hung-Chih Lin, Ching-Nen Peng | 2018-06-19 |
| 9952279 | Apparatus for three dimensional integrated circuit testing | Ching-Nen Peng, Hung-Chih Lin, Hao Chen, Chung-Han Huang, Chung-Sheng Yuan +3 more | 2018-04-24 |
| 9915699 | Integrated fan-out pillar probe system | Ching-Nen Peng, Hung-Chih Lin, Hao Chen, Mincent Lee, Chen-Hung Tien +1 more | 2018-03-13 |
| 9900970 | Three dimensional integrated circuit electrostatic discharge protection and prevention test interface | Ching-Nen Peng, Hung-Chih Lin, Hao Chen | 2018-02-20 |
| 9891266 | Test circuit and method | Ching-Nen Peng, Hung-Chih Lin, Sen-Kuei Hsu, Chuan-Ching Wang, Hao Chen | 2018-02-13 |
| 9880201 | Systems for probing semiconductor wafers | Ching-Nen Peng, Hung-Chih Lin, Hao Chen | 2018-01-30 |
| 9859176 | Semiconductor device, test system and method of the same | Tang-Jung Chiu, Hung-Chih Lin, Hao Chen | 2018-01-02 |
| 9817029 | Test probing structure | Ching-Fang Chen, Sandeep Kumar Goel, Chung-Sheng Yuan, Chao-Yang Yeh, Chin-Chou Liu +2 more | 2017-11-14 |
| 9754847 | Circuit probing structures and methods for probing the same | Ching-Nen Peng, Hung-Chih Lin, Hao Chen | 2017-09-05 |
| 9704766 | Interposers of 3-dimensional integrated circuit package systems and methods of designing the same | Sandeep Kumar Goel, Chung-Sheng Yuan, Tom C. Chen, Chao-Yang Yeh, Chin-Chou Liu +1 more | 2017-07-11 |
| 9671457 | 3D IC testing apparatus | Chih-Chia Chen, Hung-Chih Lin, Ching-Nen Peng, Hao Chen | 2017-06-06 |
| 9664707 | Testing holders for chip unit and die package | Kuo-Chuan Liu, Ching-Nen Peng, Hung-Chih Lin, Hao Chen | 2017-05-30 |
| 9658281 | Alignment testing for tiered semiconductor structure | Ching-Nen Peng, Hung-Chih Lin, Hao Chen, Mincent Lee | 2017-05-23 |