Issued Patents All Time
Showing 51–75 of 79 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9640447 | Test circuit and method | Ching-Nen Peng, Hung-Chih Lin, Hao Chen, Chung-Han Huang | 2017-05-02 |
| 9606155 | Capacitance measurement circuit and method | Ching-Nen Peng, Hung-Chih Lin, Hao Chen, Chung-Han Huang | 2017-03-28 |
| 9568543 | Structure and method for testing stacked CMOS structure | Ching-Nen Peng, Hung-Chih Lin, Hao Chen | 2017-02-14 |
| 9513332 | Probe card partition scheme | Sandeep Kumar Goel | 2016-12-06 |
| 9453877 | Testing holders for chip unit and die package | Kuo-Chuan Liu, Ching-Nen Peng, Hung-Chih Lin, Hao Chen | 2016-09-27 |
| 9448285 | Method and apparatus of wafer testing | Ching-Nen Peng, Hung-Chih Lin, Hao Chen, Shang-Ju Lee | 2016-09-20 |
| 9417285 | Integrated fan-out package-on-package testing | Ching-Nen Peng, Hung-Chih Lin, Hao Chen | 2016-08-16 |
| 9372227 | Integrated circuit test system and method | Ching-Nen Peng, Hung-Chih Lin, Wei-Hsun Lin, Hao Chen, Chung-Han Huang | 2016-06-21 |
| 9354254 | Test-yield improvement devices for high-density probing techniques and method of implementing the same | Ching-Nen Peng, Hung-Chih Lin, Wei-Hsun Lin, Sen-Kuei Hsu, De-Jian Liu | 2016-05-31 |
| 9341671 | Testing holders for chip unit and die package | Kuo-Chuan Liu, Ching-Nen Peng, Hung-Chih Lin, Hao Chen | 2016-05-17 |
| 9310437 | Adaptive test sequence for testing integrated circuits | Chun-Cheng Chen, Hung-Chih Lin, Hao Chen, Ching-Nen Peng | 2016-04-12 |
| 9252593 | Three dimensional integrated circuit electrostatic discharge protection and prevention test interface | Ching-Nen Peng, Hung-Chih Lin, Hao Chen | 2016-02-02 |
| 9234940 | Integrated fan-out wafer architecture and test method | Ching-Nen Peng, Hung-Chih Lin, Hao Chen | 2016-01-12 |
| 9129973 | Circuit probing structures and methods for probing the same | Ching-Nen Peng, Hung-Chih Lin, Hao Chen | 2015-09-08 |
| 9086452 | Three-dimensional integrated circuit and method for wireless information access thereof | Chewn-Pu Jou, Ching-Nen Peng, Huan-Neng Chen, Hung-Chih Lin, Kuang-Kai Yen +4 more | 2015-07-21 |
| 8956889 | Method of testing through silicon VIAS (TSVs) of three dimensional integrated circuit (3DIC) | Hung-Chih Lin, Ching-Nen Peng, Hao Chen | 2015-02-17 |
| 8957691 | Probe cards for probing integrated circuits | Ching-Nen Peng, Hung-Chih Lin, Hao Chen | 2015-02-17 |
| 8952711 | Methods for probing semiconductor wafers | Ching-Nen Peng, Hung-Chih Lin, Hao Chen | 2015-02-10 |
| 8922230 | 3D IC testing apparatus | Chih-Chia Chen, Hung-Chih Lin, Ching-Nen Peng, Hao Chen | 2014-12-30 |
| 8866488 | Power compensation in 3DIC testing | Ching-Nen Peng, Hung-Chih Lin, Hao Chen | 2014-10-21 |
| 8860448 | Test schemes and apparatus for passive interposers | Yun-Han Lee, Tan-Li Chou | 2014-10-14 |
| 8836355 | Dynamic testing based on thermal and stress conditions | Ching-Nen Peng, Hung-Chih Lin, Hao Chen | 2014-09-16 |
| 8836363 | Probe card partition scheme | Sandeep Kumar Goel | 2014-09-16 |
| 8742776 | Mechanisms for resistivity measurement of bump structures | You-Hua Chou, Pi-Huang Lee, Jeff Wang, Feynmann Chu | 2014-06-03 |
| 8614105 | Production flow and reusable testing method | Ching-Nen Peng, Hung-Chih Lin, Hao Chen | 2013-12-24 |