Issued Patents All Time
Showing 51–63 of 63 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7253112 | Dual damascene process | Bang-Chien Ho, Jian-Hong Chen, Tsang-Jiuh Wu, Li-Te Lin, Li-Chih Chao +1 more | 2007-08-07 |
| 6866988 | Methods for measuring photoresist dimensions | Shyue-Sheng Lu, Hong-Yuan Chu, Kuei-Shun Chen | 2005-03-15 |
| 6682858 | Method of forming small contact holes using alternative phase shift masks and negative photoresist | — | 2004-01-27 |
| 6569760 | Method to prevent poison via | Kung Linliu | 2003-05-27 |
| 6492073 | Removal of line end shortening in microlithography and mask set for removal | Burn Jeng Lin, Ru-Gun Liu, Shih-Ying Chen, Shinn-Sheng Yu, Anthony Yen +1 more | 2002-12-10 |
| 6306558 | Method of forming small contact holes using alternative phase shift masks and negative photoresist | — | 2001-10-23 |
| 6221558 | Anti-reflection oxynitride film for polysilicon substrates | Liang-Gi Yao, John Lin, Erik S. Jeng, Hsiao-Chin Tuan | 2001-04-24 |
| 6183916 | Method for proximity effect compensation on alternative phase-shift masks with bias and optical proximity correction | Chen-Cheng Kuo, Chia-Hui Lin | 2001-02-06 |
| 6133613 | Anti-reflection oxynitride film for tungsten-silicide substrates | Liang-Gi Yao, John Lin | 2000-10-17 |
| 6090674 | Method of forming a hole in the sub quarter micron range | Hung-Chang Hsieh, Jhon Jhy Liaw, Jin-Yuan Lee | 2000-07-18 |
| 6077756 | Overlay target pattern and algorithm for layer-to-layer overlay metrology for semiconductor processing | Gwo-Yuh Shiau, Pin-Ting Wang | 2000-06-20 |
| 6037276 | Method for improving patterning of a conductive layer in an integrated circuit | Erik S. Jeng, Liang-Gi Yao | 2000-03-14 |
| 5982044 | Alignment pattern and algorithm for photolithographic alignment marks on semiconductor substrates | Gwo-Yuh Shiau, Pin-Ting Wang | 1999-11-09 |