Issued Patents All Time
Showing 126–150 of 159 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6686255 | Amorphizing ion implant local oxidation of silicon (LOCOS) method for forming an isolation region | Chi-Ming Yang | 2004-02-03 |
| 6674130 | High performance PD SOI tunneling-biased MOSFET | Kuo-Nan Yang, Yi-Ling Chan, You-Lin Chu, Hou-Yu Chen, Chenming Hu | 2004-01-06 |
| 6518105 | High performance PD SOI tunneling-biased MOSFET | Kuo-Nan Yang, Yi-Ling Chan, You-Lin Chu, Hou-Yu Chen, Chenming Hu | 2003-02-11 |
| 6492216 | Method of forming a transistor with a strained channel | Yee-Chia Yeo, Chenming Hu | 2002-12-10 |
| 6277709 | Method of forming shallow trench isolation structure | Yin-Pin Wang, Chung-Ju Lee, Wen-Jya Liang, Jhy-Weei Hsia, Yuh-Sheng Chern | 2001-08-21 |
| 6278189 | High density integrated circuits using tapered and self-aligned contacts | Erik S. Jeng, Tzu-Shih Yen | 2001-08-21 |
| 6261923 | Method to solve the dishing issue in CMP planarization by using a nitride hard mask for local inverse etchback and CMP | Ming-Hong Kuo, Wei-Ray Lin | 2001-07-17 |
| 6248643 | Method of fabricating a self-aligned contact | Chien-Sheng Hsieh, Wei-Ray Lin, Erik S. Jeng, Bor-Ru Sheu | 2001-06-19 |
| 6239034 | Method of manufacturing inter-metal dielectric layers for semiconductor devices | Liang-Tung Chang | 2001-05-29 |
| 6180489 | Formation of finely controlled shallow trench isolation for ULSI process | Bih-Tiao Lin, Wei-Ray Lin, Erik S. Jeng | 2001-01-30 |
| 6174815 | Method for planarizing DRAM cells | Chau-Jen Kuo, Bin Liu | 2001-01-16 |
| 6171929 | Shallow trench isolator via non-critical chemical mechanical polishing | Chung-Ju Lee, Meow-Ru Hsu, Ming-Hong Kuo, Ing-Ruey Liaw | 2001-01-09 |
| 6159822 | Self-planarized shallow trench isolation | Chung-Ju Lee, Meow-Ru Sheu | 2000-12-12 |
| 6159821 | Methods for shallow trench isolation | Hsu-Li Cheng, Wei-Ray Lin | 2000-12-12 |
| 6140240 | Method for eliminating CMP induced microscratches | Bih-Tiao Lin, Tzu-Shih Yen, Bi-Ling Chen, Erik S. Jeng | 2000-10-31 |
| 6130127 | Method for making dynamic random access memory cells having cactus-shaped stacked capacitors with increased capacitance | — | 2000-10-10 |
| 6071789 | Method for simultaneously fabricating a DRAM capacitor and metal interconnections | Erik S. Jeng, Bih-Tiao Lin, I-Ping Lee | 2000-06-06 |
| 6060348 | Method to fabricate isolation by combining locos and shallow trench isolation for ULSI technology | Wei-Ray Lin, Ming-Hong Kuo, Erik S. Jeng | 2000-05-09 |
| 6057210 | Method of making a shallow trench isolation for ULSI formation via in-direct CMP process | Wei-Ray Lin, Ming-Hong Kuo | 2000-05-02 |
| 6054017 | Chemical mechanical polishing pad with controlled polish rate | Bih-Tiao Lin | 2000-04-25 |
| 6037259 | Method for forming identifying characters on a silicon wafer | Bih-Tiao Lin | 2000-03-14 |
| 6037216 | Method for simultaneously fabricating capacitor structures, for giga-bit DRAM cells, and peripheral interconnect structures, using a dual damascene process | Hao Liu, Wan-Yih Lien, Tzu-Shih Yen | 2000-03-14 |
| 5994228 | Method of fabricating contact holes in high density integrated circuits using taper contact and self-aligned etching processes | Erik S. Jeng, Tzu-Shih Yen | 1999-11-30 |
| 5956594 | Method for simultaneously forming capacitor plate and metal contact structures for a high density DRAM device | Bi-Ling Chen, Erik S. Jeng | 1999-09-21 |
| 5920791 | Method of manufacturing intermetal dielectrics for sub-half-micron semiconductor devices | Tony Chang | 1999-07-06 |