Issued Patents All Time
Showing 101–125 of 159 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7074656 | Doping of semiconductor fin devices | Yee-Chia Yeo, Ping-Wei Wang, Hao Chen, Chenming Hu | 2006-07-11 |
| 7053453 | Substrate contact and method of forming the same | Hsun-Chih Tsao, Chien-Chao Huang | 2006-05-30 |
| 7005330 | Structure and method for forming the gate electrode in a multiple-gate transistor | Yee-Chia Yeo | 2006-02-28 |
| 6979867 | SOI chip with mesa isolation and recess resistant regions | Yee-Chia Yeo, Hao Chen, Hsun-Chih Tsao, Chenming Hu | 2005-12-27 |
| 6974730 | Method for fabricating a recessed channel field effect transistor (FET) device | Carlos H. Diaz, Yi-Ming Sheu, Syun-Ming Jang, Hun-Jan Tao | 2005-12-13 |
| 6975006 | Semiconductor device with modified channel compressive stress | Chien-Chao Huang, Tone-Xuan Chung, Cheng-Chuan Huang | 2005-12-13 |
| 6955952 | Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement | Yee-Chia Yeo, Chun-Chieh Lin, Mong-Song Liang, Chenming Hu | 2005-10-18 |
| 6953972 | Complementary metal oxide semiconductor transistor technology using selective epitaxy of a strained silicon germanium layer | Yee-Chia Yeo, Chun-Chieh Lin, Chen Ming Hu | 2005-10-11 |
| 6906398 | Semiconductor chip with gate dielectrics for high-performance and low-leakage applications | Yee-Chia Yeo, Chenming Hu | 2005-06-14 |
| 6902962 | Silicon-on-insulator chip with multiple crystal orientations | Yee-Chia Yeo | 2005-06-07 |
| 6878610 | Relaxed silicon germanium substrate with low defect density | Chun Chich Lin, Yee-Chia Yeo, Chien-Chao Huang, Chao-Hsiung Wang, Tien-Chih Chang +4 more | 2005-04-12 |
| 6875655 | Method of forming DRAM capacitors with protected outside crown surface for more robust structures | Chun-Chieh Lin, Lan-Lin Chao, Chia-Hui Lin, Chia-Shiung Tsai, Chanming Hu | 2005-04-05 |
| 6872606 | Semiconductor device with raised segment | Hao Chen, Yee-Chia Yeo, Chenming Hu | 2005-03-29 |
| 6867433 | Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors | Yee-Chia Yeo, How-Yu Chen, Chien-Chao Huang, Wen-Chin Lee, Chenming Hu | 2005-03-15 |
| 6864149 | SOI chip with mesa isolation and recess resistant regions | Yee-Chia Yeo, Hao Chen, Hsun-Chih Tsao, Chenming Hu | 2005-03-08 |
| 6864519 | CMOS SRAM cell configured using multiple-gate transistors | Yee-Chia Yeo, Chenming Hu | 2005-03-08 |
| 6855606 | Semiconductor nano-rod devices | Hao Chen, Yee-Chia Yeo, Chenming Hu | 2005-02-15 |
| 6855990 | Strained-channel multiple-gate transistor | Yee-Chia Yeo, Chenming Hu | 2005-02-15 |
| 6844238 | Multiple-gate transistors with improved gate control | Yee-Chia Yeo, Chenming Hu | 2005-01-18 |
| 6835967 | Semiconductor diodes with fin structure | Yee-Chia Yeo | 2004-12-28 |
| 6800516 | Electrostatic discharge device protection structure | Yi-Ling Chan, Yi-Ming Sheu | 2004-10-05 |
| 6784071 | Bonded SOI wafer with <100> device layer and <110> substrate for performance improvement | Haur-Ywh Chen, Yi-Ling Chan, Kuo-Nan Yang, Chenming Hu | 2004-08-31 |
| 6720619 | Semiconductor-on-insulator chip incorporating partially-depleted, fully-depleted, and multiple-gate devices | Hao Chen, Yee-Chia Yeo, Chenming Hu | 2004-04-13 |
| 6703271 | Complementary metal oxide semiconductor transistor technology using selective epitaxy of a strained silicon germanium layer | Yee-Chia Yeo, Chun-Chieh Lin, Chen Ming Hu | 2004-03-09 |
| 6703187 | Method of forming a self-aligned twin well structure with a single mask | Yi-Ming Sheu | 2004-03-09 |