Issued Patents All Time
Showing 76–100 of 159 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7262086 | Contacts to semiconductor fin devices | Yee-Chia Yeo, Chenming Hu | 2007-08-28 |
| 7247922 | Inductor energy loss reduction techniques | Andrew S. Yeh, Alex Chang, Sung-Pi Tseng, Chang-Yun Chang, Hao Chen | 2007-07-24 |
| 7244640 | Method for fabricating a body contact in a Finfet structure and a device including the same | Kuo-Nan Yang, Yi Chen, Hou-Yu Chen, Chenming Hu | 2007-07-17 |
| 7238989 | Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement | Yee-Chia Yeo, Chun-Chieh Lin, Mong-Song Liang, Chenming Hu | 2007-07-03 |
| 7230270 | Self-aligned double gate device and method for forming same | Hao Chen, Ju-Wang Hsu, Baw-Ching Perng | 2007-06-12 |
| 7226832 | Complementary metal oxide semiconductor transistor technology using selective epitaxy of a strained silicon germanium layer | Yee-Chia Yeo, Chun-Chieh Lin, Chen Ming Hu | 2007-06-05 |
| 7214991 | CMOS inverters configured using multiple-gate transistors | Yee-Chia Yeo, Chenming Hu | 2007-05-08 |
| 7208815 | CMOS logic gate fabricated on hybrid crystal orientations and method of forming thereof | Hung-Wei Chen, Ping-Kun Wu, Chao-Hsiung Wang, Chenming Hu | 2007-04-24 |
| 7202139 | MOSFET device with a strained channel | Yee-Chia Yeo, Chen Ming Hu | 2007-04-10 |
| 7187000 | High performance tunneling-biased MOSFET and a process for its manufacture | Kuo-Nan Yang, Yi-Ling Chang, You-Lin Chu, Hou-Yu Chen, Chenming Hu | 2007-03-06 |
| 7183137 | Method for dicing semiconductor wafers | Hsin-Hui Lee, Chien-Chao Huang, Chao-Hsiung Wang, Chenming Hu | 2007-02-27 |
| 7180134 | Methods and structures for planar and multiple-gate transistors formed on SOI | Yee-Chia Yeo, Chenming Hu | 2007-02-20 |
| 7176092 | Gate electrode for a semiconductor fin device | Yee-Chia Yeo, Hao Chen, Chenming Hu | 2007-02-13 |
| 7176084 | Self-aligned conductive spacer process for sidewall control gate of high-speed random access memory | Tzyh-Cheang Lee, Jiunn-Ren Hwang, Tsung-Lin Lee | 2007-02-13 |
| 7172943 | Multiple-gate transistors formed on bulk substrates | Yee-Chia Yeo, Chenming Hu | 2007-02-06 |
| 7173305 | Self-aligned contact for silicon-on-insulator devices | Yee-Chia Yeo, Horng-Huei Tseng, Chenming Hu | 2007-02-06 |
| 7170118 | Field effect transistor (FET) device having corrugated structure and method for fabrication thereof | — | 2007-01-30 |
| 7164189 | Slim spacer device and manufacturing method | Chien-Chao Huang, Tone-Xuan Chung | 2007-01-16 |
| 7161204 | DRAM capacitor structure with increased electrode support for preventing process damage and exposed electrode surface for increasing capacitor area | Chun-Chieh Lin, Lan-Lin Chao, Chia-Shiung Tsai, Chia-Hui Lin, Chanming Hu | 2007-01-09 |
| 7141459 | Silicon-on-insulator ULSI devices with multiple silicon film thicknesses | Hao Chen, Yee-Chia Yeo, Carlos H. Diaz, Chenming Hu | 2006-11-28 |
| 7135372 | Strained silicon device manufacturing method | Chien-Chao Huang, Cheng-Chuan Huang | 2006-11-14 |
| 7125759 | Semiconductor-on-insulator (SOI) strained active areas | Hao Chen | 2006-10-24 |
| 7122412 | Method of fabricating a necked FINFET device | Haur-Ywh Chen, Fang Chen, Yi-Ling Chan, Kuo-Nan Yang, Chenming Hu | 2006-10-17 |
| 7105894 | Contacts to semiconductor fin devices | Yee-Chia Yeo, Chenming Hu | 2006-09-12 |
| 7105897 | Semiconductor structure and method for integrating SOI devices and bulk devices | Hao Chen, Hung-Wei Chen, Ping-Kun Wu, Chao-Hsiung Wang | 2006-09-12 |