Issued Patents All Time
Showing 126–150 of 164 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6812116 | Method of fabricating a wafer with strained channel layers for increased electron and hole mobility for improving device performance | Chien-Chao Huang, Yee-Chia Yeo, Kuo-Nan Yang, Chun-Chieh Lin | 2004-11-02 |
| RE38608 | Low-voltage punch-through transient suppressor employing a dual-base structure | Bin Yu, Ya-Chin King, Jeffrey T. Pohlman, Rita Trivedi | 2004-10-05 |
| 6794234 | Dual work function CMOS gate technology based on metal interdiffusion | Igor Polishchuk, Pushkar Ranade, Tsu-Jae King | 2004-09-21 |
| 6784071 | Bonded SOI wafer with <100> device layer and <110> substrate for performance improvement | Haur-Ywh Chen, Yi-Ling Chan, Kuo-Nan Yang, Fu-Liang Yang | 2004-08-31 |
| 6720619 | Semiconductor-on-insulator chip incorporating partially-depleted, fully-depleted, and multiple-gate devices | Hao Chen, Yee-Chia Yeo, Fu-Liang Yang | 2004-04-13 |
| 6674130 | High performance PD SOI tunneling-biased MOSFET | Kuo-Nan Yang, Yi-Ling Chan, You-Lin Chu, Hou-Yu Chen, Fu-Liang Yang | 2004-01-06 |
| 6627515 | Method of fabricating a non-floating body device with enhanced performance | Horng-Huei Tseng, Jyh-Chyurn Guo, Da-Chi Lin | 2003-09-30 |
| 6603187 | Antifuse structure suitable for VLSI application | Guobiao ZHANG, Steve S. Chiang | 2003-08-05 |
| 6518105 | High performance PD SOI tunneling-biased MOSFET | Kuo-Nan Yang, Yi-Ling Chan, You-Lin Chu, Hou-Yu Chen, Fu-Liang Yang | 2003-02-11 |
| 6492216 | Method of forming a transistor with a strained channel | Yee-Chia Yeo, Fu-Liang Yang | 2002-12-10 |
| 6413802 | Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture | Tsu-Jae King, Vivek Subramanian, Leland Chang, Xuejue Huang, Yang-Kyu Choi +4 more | 2002-07-02 |
| 6344404 | Method of separation films from bulk substrates by plasma immersion ion implantation | Nathan W. Cheung, Xiang Lu | 2002-02-05 |
| 6300649 | Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibility | Mansun Chan, Hsing-Jen Wann, Ping Keung Ko | 2001-10-09 |
| 6121077 | Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibility | Mansun Chan, Hsing-Jen Wann, Ping Keung Ko | 2000-09-19 |
| 6111302 | Antifuse structure suitable for VLSI application | Guobiao ZHANG, Steve S. Chiang | 2000-08-29 |
| 6027988 | Method of separating films from bulk substrates by plasma immersion ion implantation | Nathan W. Cheung, Xiang Lu | 2000-02-22 |
| 6015999 | Low-voltage punch-through transient suppressor employing a dual-base structure | Bin Yu, Ya-Chin King, Jeffrey T. Pohlman, Rita Trivedi | 2000-01-18 |
| 6005409 | Detection of process-induced damage on transistors in real time | Nguyen Duc Bui, Donggun Park, Scott Zheng | 1999-12-21 |
| 5982003 | Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibility | Mansun Chan, Hsing-Jen Wann, Ping Keung Ko | 1999-11-09 |
| 5880511 | Low-voltage punch-through transient suppressor employing a dual-base structure | Bin Yu, Ya-Chin King, Jeffrey T. Pohlman, Rita Trivedi | 1999-03-09 |
| 5790436 | Realistic worst-case circuit simulation system and method | James Chieh-Tsung Chen, Zhihong Liu, Ping Keung Ko | 1998-08-04 |
| 5780899 | Delta doped and counter doped dynamic threshold voltage MOSFET for ultra-low voltage operation | Hsing-Jen Wann | 1998-07-14 |
| 5768182 | Ferroelectric nonvolatile dynamic random access memory device | Reza Moazzami | 1998-06-16 |
| 5670818 | Electrically programmable antifuse | Abdul Rahim Forouhi, Esmat Z. Hamdy, John McCollum | 1997-09-23 |
| 5631485 | ESD and hot carrier resistant integrated circuit structure | Yi Wei, Ying-Tsong Loh, Chung S. Wang | 1997-05-20 |