Issued Patents All Time
Showing 76–100 of 164 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7183593 | Heterostructure resistor and method of forming the same | Yee-Chia Yeo, Wen-Chin Lee, Chih-Hsin Ko, Chung-Hu Ge, Chun-Chieh Lin | 2007-02-27 |
| 7180134 | Methods and structures for planar and multiple-gate transistors formed on SOI | Fu-Liang Yang, Yee-Chia Yeo | 2007-02-20 |
| 7176092 | Gate electrode for a semiconductor fin device | Yee-Chia Yeo, Hao Chen, Fu-Liang Yang | 2007-02-13 |
| 7173305 | Self-aligned contact for silicon-on-insulator devices | Fu-Liang Yang, Yee-Chia Yeo, Horng-Huei Tseng | 2007-02-06 |
| 7172943 | Multiple-gate transistors formed on bulk substrates | Yee-Chia Yeo, Fu-Liang Yang | 2007-02-06 |
| 7167109 | Hybrid fractional-bit systems | Guobiao ZHANG | 2007-01-23 |
| 7157774 | Strained silicon-on-insulator transistors with mesa isolation | Yee-Chia Yeo | 2007-01-02 |
| 7141459 | Silicon-on-insulator ULSI devices with multiple silicon film thicknesses | Fu-Liang Yang, Hao Chen, Yee-Chia Yeo, Carlos H. Diaz | 2006-11-28 |
| 7141858 | Dual work function CMOS gate technology based on metal interdiffusion | Igor Polishchuk, Pushkar Ranade, Tsu-Jae King | 2006-11-28 |
| 7126225 | Apparatus and method for manufacturing a semiconductor wafer with reduced delamination and peeling | Chao-Yuan Su, Pei-Haw Tsao, Hsin-Hui Lee, Chender Huang, Shang Y. Hou +2 more | 2006-10-24 |
| 7122412 | Method of fabricating a necked FINFET device | Haur-Ywh Chen, Fang Chen, Yi-Ling Chan, Kuo-Nan Yang, Fu-Liang Yang | 2006-10-17 |
| 7112495 | Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit | Chih-Hsin Ko, Wen-Chin Lee, Yee-Chia Yeo, Chun-Chieh Lin | 2006-09-26 |
| 7112483 | Method for forming a device having multiple silicide types | Chun-Chieh Lin, Wen-Chin Lee, Yee-Chia Yeo, Chuan-Yi Lin | 2006-09-26 |
| 7105894 | Contacts to semiconductor fin devices | Yee-Chia Yeo, Fu-Liang Yang | 2006-09-12 |
| 7105928 | Copper wiring with high temperature superconductor (HTS) layer | Chen-Hua Yu, Horng-Huei Tseng, Chao-Hsiung Wang | 2006-09-12 |
| 7101742 | Strained channel complementary field-effect transistors and methods of manufacture | Chih-Hsin Ko, Yee-Chia Yeo, Wen-Chin Lee | 2006-09-05 |
| 7098119 | Thermal anneal process for strained-Si devices | Chung-Hu Ke, Wen-Chin Lee | 2006-08-29 |
| 7081395 | Silicon strain engineering accomplished via use of specific shallow trench isolation fill materials | Min-hwa Chi, Yee-Chia Yeo | 2006-07-25 |
| 7074656 | Doping of semiconductor fin devices | Yee-Chia Yeo, Ping-Wei Wang, Hao Chen, Fu-Liang Yang | 2006-07-11 |
| 7071052 | Resistor with reduced leakage | Yee-Chia Yeo | 2006-07-04 |
| 7057237 | Method for forming devices with multiple spacer widths | Howard Chih-Hao Wang, Chun-Chieh Lin | 2006-06-06 |
| 7052964 | Strained channel transistor and methods of manufacture | Yee-Chia Yeo, Chih-Hsin Ko, Wen-Chin Lee | 2006-05-30 |
| 7045836 | Semiconductor structure having a strained region and a method of fabricating same | Wen-Chin Lee, Chung-Hu Ge | 2006-05-16 |
| 7045847 | Semiconductor device with high-k gate dielectric | Chun-Chieh Lin, Wen-Chin Lee, Shang-Chih Chen, Chih-Hao Wang, Fu-Liaog Yang +1 more | 2006-05-16 |
| 7037772 | Method of manufacturing an integrated circuit including capacitor with high permittivity capacitor dielectric | Yee-Chia Yeo | 2006-05-02 |