Issued Patents All Time
Showing 51–75 of 164 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7442967 | Strained channel complementary field-effect transistors | Chih-Hsin Ko, Yee-Chia Yeo, Wen-Chin Lee | 2008-10-28 |
| 7423323 | Semiconductor device with raised segment | Hao Chen, Yee-Chia Yeo, Fu-Liang Yang | 2008-09-09 |
| 7394136 | High performance semiconductor devices fabricated with strain-induced processes and methods for making same | Chung-Hu Ke, Wen-Chin Lee, Yee-Chia Yeo, Chih-Hsin Ko | 2008-07-01 |
| 7372107 | SOI chip with recess-resistant buried insulator and method of manufacturing the same | Yee-Chia Yeo | 2008-05-13 |
| 7357838 | Relaxed silicon germanium substrate with low defect density | Chun-Chieh Lin, Yee-Chia Yeo, Chien-Chao Huang, Chao-Hsiung Wang, Tien-Chih Chang +4 more | 2008-04-15 |
| 7354843 | Method of forming a capacitor that includes forming a bottom electrode in a strained silicon layer | Yee-Chia Yeo | 2008-04-08 |
| 7354830 | Methods of forming semiconductor devices with high-k gate dielectric | Chun-Chieh Lin, Wen-Chin Lee, Shang-Chih Chen, Chih-Hao Wang, Fu-Liaog Yang +1 more | 2008-04-08 |
| 7342289 | Strained silicon MOS devices | Chien-Chao Huang, Chung-Hu Ge, Wen-Chin Lee, Carlos H. Diaz, Fu-Liang Yang | 2008-03-11 |
| 7335929 | Transistor with a strained region and method of manufacture | Chun-Chieh Lin, Wen-Chin Lee, Yee-Chia Yeo | 2008-02-26 |
| 7319258 | Semiconductor-on-insulator chip with<100>-oriented transistors | Fu-Liang Yang, Yee-Chia Yeo, Hung-Wei Chen, Tim Tsao | 2008-01-15 |
| 7312136 | Method of fabricating a wafer with strained channel layers for increased electron and hole mobility for improving device performance | Chien-Chao Huang, Yee-Chia Yeo, Kuo-Nan Yang, Chun-Chieh Lin | 2007-12-25 |
| 7301206 | Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors | Yee-Chia Yeo, Fu-Liang Yang | 2007-11-27 |
| 7294937 | Apparatus and method for manufacturing a semiconductor wafer with reduced delamination and peeling | Chao-Yuan Su, Pei-Haw Tsao, Hsin-Hui Lee, Chender Huang, Shang Y. Hou +2 more | 2007-11-13 |
| 7279756 | Semiconductor device with high-k gate dielectric and quasi-metal gate, and method of forming thereof | Chih-Hao Wang, Ching-Wei Tsai | 2007-10-09 |
| 7268024 | Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors | Yee-Chia Yeo, How-Yu Chen, Chien-Chao Huang, Wen-Chin Lee, Fu-Liang Yang | 2007-09-11 |
| 7265447 | Interconnect with composite layers and method for fabricating the same | Chen-Hua Yu, Horng-Huei Tseng, Syun-Ming Jang | 2007-09-04 |
| 7262086 | Contacts to semiconductor fin devices | Yee-Chia Yeo, Fu-Liang Yang | 2007-08-28 |
| 7244640 | Method for fabricating a body contact in a Finfet structure and a device including the same | Kuo-Nan Yang, Yi Chen, Hou-Yu Chen, Fu-Liang Yang | 2007-07-17 |
| 7238989 | Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement | Yee-Chia Yeo, Chun-Chieh Lin, Fu-Liang Yang, Mong-Song Liang | 2007-07-03 |
| 7214991 | CMOS inverters configured using multiple-gate transistors | Yee-Chia Yeo, Fu-Liang Yang | 2007-05-08 |
| 7208815 | CMOS logic gate fabricated on hybrid crystal orientations and method of forming thereof | Hung-Wei Chen, Ping-Kun Wu, Chao-Hsiung Wang, Fu-Liang Yang | 2007-04-24 |
| 7208754 | Strained silicon structure | Chung-Hu Ge, Wen-Chin Lee | 2007-04-24 |
| 7202122 | Cobalt silicidation process for substrates with a silicon—germanium layer | Chien-Chao Huang, Yee-Chia Yeo, Chao-Hsiung Wang, Chun-Chieh Lin | 2007-04-10 |
| 7187000 | High performance tunneling-biased MOSFET and a process for its manufacture | Kuo-Nan Yang, Yi-Ling Chang, You-Lin Chu, Hou-Yu Chen, Fu-Liang Yang | 2007-03-06 |
| 7183593 | Heterostructure resistor and method of forming the same | Yee-Chia Yeo, Wen-Chin Lee, Chih-Hsin Ko, Chung-Hu Ge, Chun-Chieh Lin | 2007-02-27 |