CH

Chender Huang

TSMC: 22 patents #1,516 of 12,232Top 15%
Micron: 6 patents #2,080 of 6,345Top 35%
📍 Boise, ID: #353 of 3,546 inventorsTop 10%
🗺 Idaho: #490 of 8,810 inventorsTop 6%
Overall (All Time): #132,245 of 4,157,543Top 4%
29
Patents All Time

Issued Patents All Time

Showing 1–25 of 29 patents

Patent #TitleCo-InventorsDate
8685834 Fabrication method of package structure with simplified encapsulation structure and simplified wiring Pei-Haw Tsao, Chuen-Jye Lin 2014-04-01
7638887 Package structure and fabrication method thereof Pei-Haw Tsao, Chuen-Jye Lin 2009-12-29
7443010 Matrix form semiconductor package substrate having an electrode of serpentine shape Pei-Haw Tsao, Chung Yu Wang 2008-10-28
7390697 Enhanced adhesion strength between mold resin and polyimide Ken-Ching Chen, Pei-Haw Tsao, Jones Wang, Hank Huang 2008-06-24
7378731 Heat spreader and package structure utilizing the same Pei-Haw Tsao, Allan Lin, Jeffrey Hsu 2008-05-27
7294937 Apparatus and method for manufacturing a semiconductor wafer with reduced delamination and peeling Chao-Yuan Su, Pei-Haw Tsao, Hsin-Hui Lee, Shang Y. Hou, Shin-Puu Jeng +2 more 2007-11-13
7190066 Heat spreader and package structure utilizing the same Pei-Haw Tsao, Allan Lin, Jeffrey Hsu 2007-03-13
7157734 Semiconductor bond pad structures and methods of manufacturing thereof Pei-Haw Tsao, Shang Y. Hou, Chao-Yuan Su, Chia-Hsiung Hsu 2007-01-02
7126225 Apparatus and method for manufacturing a semiconductor wafer with reduced delamination and peeling Chao-Yuan Su, Pei-Haw Tsao, Hsin-Hui Lee, Shang Y. Hou, Shin-Puu Jeng +2 more 2006-10-24
7026711 Thermal dispensing enhancement for high performance flip chip BGA (HPFCBGA) Daniel Lee, Chien-Hsiun Lee 2006-04-11
7015066 Method for stress reduction in flip chip bump during flip chip mounting and underfill process steps of making a microelectronic assembly Pei-Haw Tsao, Jones Wang, Ken-Ching Chen 2006-03-21
6998860 Method for burn-in testing semiconductor dice Alan G. Wood, Tim J. Corbett, Gary L. Chadwick, Larry D. Kinsman 2006-02-14
6960518 Buildup substrate pad pre-solder bump manufacturing Pei-Haw Tsao, Jones Wang, Ken-Ching Chen, Hank Huang 2005-11-01
6939789 Method of wafer level chip scale packaging Pei-Haw Tsao, Jones Wang, Ken-Ching Chen 2005-09-06
6884662 Enhanced adhesion strength between mold resin and polyimide Ken-Ching Chen, Pei-Haw Tsao, Jones Wang, Hank Huang 2005-04-26
6782897 Method of protecting a passivation layer during solder bump formation Chung Yu Wang, Pei-Haw Tsao, Ken-Ching Chen, Hank Huang 2004-08-31
6774026 Structure and method for low-stress concentration solder bumps Chung Yu Wang, Pei-Haw Tsao, Ken-Ching Chen, Hank Huang 2004-08-10
6770958 Under bump metallization structure Chung Yu Wang, Pei-Haw Tsao, Ken-Ching Chen, Hank Huang 2004-08-03
6656827 Electrical performance enhanced wafer level chip scale package with ground Pei-Haw Tsao, Jones Wang, Ken-Ching Chen, Hank Huang 2003-12-02
6638837 Method for protecting the front side of semiconductor wafers Pei-Haw Tsao, Jones Wang, Ken-Ching Chen, Hank Huang 2003-10-28
6596619 Method for fabricating an under bump metallization structure Chung Yu Wang, Pei-Haw Tsao, Ken-Ching Chen, Hank Huang 2003-07-22
6528417 Metal patterned structure for SiN surface adhesion enhancement Chung Yu Wang, Pei-Haw Tsao, Ken-Ching Chen 2003-03-04
6372619 Method for fabricating wafer level chip scale package with discrete package encapsulation Pei-Hwa Tsao 2002-04-16
6091251 Discrete die burn-in for nonpackaged die Alan G. Wood, Tim J. Corbett, Gary L. Chadwick, Larry D. Kinsman 2000-07-18
6091250 Discrete die burn-in for nonpackaged die Alan G. Wood, Tim J. Corbett, Gary L. Chadwick, Larry D. Kinsman 2000-07-18