Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5821558 | Antifuse structures | Yu-Pin Han, Ivan Sanchez | 1998-10-13 |
| 5793094 | Methods for fabricating anti-fuse structures | Ivan Sanchez, Yu-Pin Han, Walter D. Parmantie | 1998-08-11 |
| 5793640 | Capacitance measurement using an RLC circuit model | Koucheng Wu, Yu-Pin Han | 1998-08-11 |
| 5789795 | Methods and apparatus for fabricationg anti-fuse devices | Ivan Sanchez, Yu-Pin Han, Miguel A. Delgado | 1998-08-04 |
| 5783467 | Method of making antifuse structures using implantation of both neutral and dopant species | Yu-Pin Han, Ivan Sanchez | 1998-07-21 |
| 5773317 | Test structure and method for determining metal-oxide-silicon field effect transistor fringing capacitance | Koucheng Wu, Yu-Pin Han | 1998-06-30 |
| 5759901 | Fabrication method for sub-half micron CMOS transistor | Lily Ding | 1998-06-02 |
| 5753540 | Apparatus and method for programming antifuse structures | Koucheng Wu, Ivan Sanchez, Yu-Pin Han | 1998-05-19 |
| 5700717 | Method of reducing contact resistance for semiconductor manufacturing processes using tungsten plugs | Edward D. Nowak, Lily Ding | 1997-12-23 |
| 5631485 | ESD and hot carrier resistant integrated circuit structure | Yi Wei, Chung S. Wang, Chenming Hu | 1997-05-20 |
| 5516707 | Large-tilted-angle nitrogen implant into dielectric regions overlaying source/drain regions of a transistor | Lily Ding, Edward D. Nowak | 1996-05-14 |
| 5496751 | Method of forming an ESD and hot carrier resistant integrated circuit structure | Yi Wei, Chung S. Wang, Chenming Hu | 1996-03-05 |
| 5444003 | Method and structure for creating a self-aligned bicmos-compatible bipolar transistor with a laterally graded emitter structure | Chung S. Wang, Ho-Yuan Yu | 1995-08-22 |
| 5411906 | Method of fabricating auxiliary gate lightly doped drain (AGLDD) structure with dielectric sidewalls | Eric A. Johnson, Chung S. Wang | 1995-05-02 |
| 5340761 | Self-aligned contacts with gate overlapped lightly doped drain (goldd) structure | Chung S. Wang | 1994-08-23 |
| 5288652 | BICMOS-compatible method for creating a bipolar transistor with laterally graded emitter structure | Chung S. Wang, Edward D. Nowak | 1994-02-22 |
| 5227320 | Method for producing gate overlapped lightly doped drain (GOLDD) structure for submicron transistor | Eric A. Johnson, Yoshiko H. Strunk, Chung S. Wang | 1993-07-13 |
| 5196357 | Method of making extended polysilicon self-aligned gate overlapped lightly doped drain structure for submicron transistor | William J. Boardman, Edward D. Nowak, Chung S. Wang | 1993-03-23 |