Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11903331 | Digital circuits comprising quantum wire resonant tunneling transistors | — | 2024-02-13 |
| 11496072 | Device and method for work function reduction and thermionic energy conversion | — | 2022-11-08 |
| 11133384 | Quantum wire resonant tunneling transistor | — | 2021-09-28 |
| 8237212 | Nonvolatile memory with a unified cell structure | Peter Wung Lee, Fu-Chang Hsu, Hsing-Ya Tsao, Han-Rei Ma | 2012-08-07 |
| 7936040 | Schottky barrier quantum well resonant tunneling transistor | — | 2011-05-03 |
| 7915092 | Nonvolatile memory with a unified cell structure | Peter Wung Lee, Fu-Chang Hsu, Hsing-Ya Tsao, Han-Rei Ma | 2011-03-29 |
| 7636252 | Nonvolatile memory with a unified cell structure | Peter Wung Lee, Fu-Chang Hsu, Hsing-Ya Tsao, Han-Rei Ma | 2009-12-22 |
| 7495283 | Nor-type channel-program channel-erase contactless flash memory on SOI | — | 2009-02-24 |
| 7324384 | Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout | Peter Wung Lee, Fu-Chang Hsu, Hsing-Ya Tsao, Han-Rei Ma | 2008-01-29 |
| 7120064 | Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout | Peter Wung Lee, Fu-Chang Hsu, Hsing-Ya Tsao, Han-Rei Ma | 2006-10-10 |
| 7110302 | Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout | Peter Wung Lee, Fu-Chang Hsu, Hsing-Ya Tsao, Han-Rei Ma | 2006-09-19 |
| 7102929 | Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout | Peter Wung Lee, Fu-Chang Hsu, Hsing-Ya Tsao, Han-Rei Ma | 2006-09-05 |
| 7075826 | Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout | Peter Wung Lee, Fu-Chang Hsu, Hsing-Ya Tsao, Han-Rei Ma | 2006-07-11 |
| 7042044 | Nor-type channel-program channel-erase contactless flash memory on SOI | — | 2006-05-09 |
| 6963121 | Schottky-barrier tunneling transistor | — | 2005-11-08 |
| 6862223 | MONOLITHIC, COMBO NONVOLATILE MEMORY ALLOWING BYTE, PAGE AND BLOCK WRITE WITH NO DISTURB AND DIVIDED-WELL IN THE CELL ARRAY USING A UNIFIED CELL STRUCTURE AND TECHNOLOGY WITH A NEW SCHEME OF DECODER AND LAYOUT | Peter Wung Lee, Fu-Chang Hsu, Hsing-Ya Tsao, Han-Rei Ma | 2005-03-01 |
| 6744111 | Schottky-barrier tunneling transistor | — | 2004-06-01 |
| 6087677 | High density self-aligned antifuse | — | 2000-07-11 |
| 6005810 | Byte-programmable flash memory having counters and secondary storage for disturb control during program and erase operations | — | 1999-12-21 |
| 5793640 | Capacitance measurement using an RLC circuit model | Yu-Pin Han, Ying-Tsong Loh | 1998-08-11 |
| 5773317 | Test structure and method for determining metal-oxide-silicon field effect transistor fringing capacitance | Yu-Pin Han, Ying-Tsong Loh | 1998-06-30 |
| 5753540 | Apparatus and method for programming antifuse structures | Ivan Sanchez, Yu-Pin Han, Ying-Tsong Loh | 1998-05-19 |