Issued Patents All Time
Showing 25 most recent of 191 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10600793 | Fabricating memory devices with optimized gate oxide thickness | Runzi Chang, Winston Lee | 2020-03-24 |
| 10319727 | Fabricating memory devices with optimized gate oxide thickness | Runzi Chang, Winston Lee | 2019-06-11 |
| 10037290 | Dual-port memories and input/output circuits for preventing failures corresponding to concurrent accesses of dual-port memory cells | Moon-Hae Son, Xinghui Guo | 2018-07-31 |
| 10037400 | Integrated circuit manufacturing process for aligning threshold voltages of transistors | Runzi Chang, Winston Lee | 2018-07-31 |
| 9830976 | Systems and methods for a high performance memory cell structure | Winston Lee | 2017-11-28 |
| 9666286 | Self-timed SLC NAND pipeline and concurrent program without verification | — | 2017-05-30 |
| 9659636 | NAND memory array with BL-hierarchical structure for concurrent all-BL, all-threshold-state program, and alternative-WL program, odd/even read and verify operations | — | 2017-05-23 |
| 9613704 | 2D/3D NAND memory array with bit-line hierarchical structure for multi-page concurrent SLC/MLC program and program-verify | — | 2017-04-04 |
| 9595319 | Partial/full array/block erase for 2D/3D hierarchical NAND | — | 2017-03-14 |
| 9558811 | Disturb-proof static RAM cells | Winston Lee, Donald Lee | 2017-01-31 |
| 9530492 | NAND array hiarchical BL structures for multiple-WL and All-BL simultaneous erase, erase-verify, program, program-verify, and read operations | — | 2016-12-27 |
| 9524773 | Multi-task concurrent/pipeline NAND operations on all planes | — | 2016-12-20 |
| 9490427 | Resistive random access memory cell structure | Pantas Sutardja, Albert Wu, Winston Lee, Runzi Chang | 2016-11-08 |
| 9443579 | VSL-based VT-compensation and analog program scheme for NAND array without CSL | — | 2016-09-13 |
| 9443578 | NAND array architecture for multiple simultaneous program and read | — | 2016-09-13 |
| 9437306 | NAND array architecture for multiple simutaneous program and read | — | 2016-09-06 |
| 9424911 | Method and apparatus for screening memory cells for disturb failures | Winston Lee, Moon-Hae Son | 2016-08-23 |
| 9324417 | Systems and methods for avoiding read disturbance in a static random-access memory (SRAM) | Winston Lee | 2016-04-26 |
| 9293205 | Multi-task concurrent/pipeline NAND operations on all planes | — | 2016-03-22 |
| 9275731 | Systems and methods for increasing the read sensitivity of a resistive random access memory (RRAM) | Pantas Sutardja, Albert Wu, Runzi Chang, Winston Lee | 2016-03-01 |
| 9263137 | NAND array architecture for multiple simutaneous program and read | — | 2016-02-16 |
| 9245961 | Reducing source contact to gate spacing to decrease transistor pitch | Albert Wu, Pantas Sutardja, Winston Lee, Chien-Chuan Wei, Runzi Chang | 2016-01-26 |
| 9230677 | NAND array hiarchical BL structures for multiple-WL and all-BL simultaneous erase, erase-verify, program, program-verify, and read operations | — | 2016-01-05 |
| 9214230 | Resistive random access memory cell structure with reduced programming voltage | Pantas Sutardja, Albert Wu, Winston Lee, Runzi Chang | 2015-12-15 |
| 9183940 | Low disturbance, power-consumption, and latency in NAND read and program-verify operations | — | 2015-11-10 |