Issued Patents All Time
Showing 26–50 of 191 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9177658 | 1T1b and 2T2b flash-based, data-oriented EEPROM design | Hsing-Ya Tsao | 2015-11-03 |
| 9177645 | 10T NVSRAM cell and cell operations | Hsing-Ya Tsao | 2015-11-03 |
| 9177644 | Low-voltage fast-write PMOS NVSRAM cell | Hsing-Ya Tsao | 2015-11-03 |
| 9171627 | Non-boosting program inhibit scheme in NAND design | Hsing-Ya Tsao | 2015-10-27 |
| 9147837 | Resistive memory cell and method for forming a resistive memory cell | Pantas Sutardja, Albert Wu, Winston Lee, Runzi Chang | 2015-09-29 |
| 9142284 | Concurrent use of SRAM cells with both NMOS and PMOS pass gates in a memory system | Winston Lee | 2015-09-22 |
| 9129678 | Method and apparatus for reforming a memory cell of a memory | Pantas Sutardja, Albert Wu, Winston Lee, Runzi Chang | 2015-09-08 |
| 9112133 | Resistive random access memory and method for controlling manufacturing of corresponding sub-resolution features of conductive and resistive elements | Pantas Sutardja, Albert Wu, Runzi Chang, Winston Lee | 2015-08-18 |
| 9087595 | Shielding 2-cycle half-page read and program schemes for advanced NAND flash design | — | 2015-07-21 |
| 9063849 | Different types of memory integrated in one chip by using a novel protocol | Fu-Chang Hsu | 2015-06-23 |
| 9047945 | Systems and methods for reading resistive random access memory (RRAM) cells | Pantas Sutardja, Albert Wu, Runzi Chang, Winston Lee | 2015-06-02 |
| 9042162 | SRAM cells suitable for Fin field-effect transistor (FinFET) process | Winston Lee | 2015-05-26 |
| 9042159 | Configuring resistive random access memory (RRAM) array for write operations | Pantas Sutardja, Albert Wu, Runzi Chang, Winston Lee | 2015-05-26 |
| 9019764 | Low-voltage page buffer to be used in NVM design | Hsing-Ya Tsao | 2015-04-28 |
| 9001583 | On-chip HV and LV capacitors acting as the second back-up supplies for NVSRAM auto-store operation | Hsing-Ya Tsao | 2015-04-07 |
| 9001545 | NOR-based BCAM/TCAM cell and array with NAND scalability | — | 2015-04-07 |
| 8999786 | Reducing source contact to gate spacing to decrease transistor pitch | Albert Wu, Pantas Sutardja, Winston Lee, Chien-Chuan Wei, Runzi Chang | 2015-04-07 |
| 8996785 | NAND-based hybrid NVM design that integrates NAND and NOR in 1-die with serial interface | Fu-Chang Hsu, Kesheng Wang | 2015-03-31 |
| 8976588 | NVSRAM cells with voltage flash charger | — | 2015-03-10 |
| 8971113 | Pseudo-8T NVSRAM cell with a charge-follower | — | 2015-03-03 |
| 8964470 | Method and architecture for improving defect detectability, coupling area, and flexibility of NVSRAM cells and arrays | — | 2015-02-24 |
| 8947909 | System and method for creating a bipolar resistive RAM (RRAM) | Pantas Sutardja, Albert Wu, Winston Lee, Runzi Chang | 2015-02-03 |
| 8937831 | System and method for modifying activation of a sense amplifier | Moon-Hae Son, Winston Lee | 2015-01-20 |
| 8934285 | Method and apparatus for forming a contact in a cell of a resistive random access memory to reduce a voltage required to program the cell | Pantas Sutardja, Albert Wu, Winston Lee, Runzi Chang | 2015-01-13 |
| 8933749 | Circuits and methods for calibrating offset in an amplifier | Winston Lee | 2015-01-13 |