Issued Patents All Time
Showing 51–75 of 191 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8934285 | Method and apparatus for forming a contact in a cell of a resistive random access memory to reduce a voltage required to program the cell | Pantas Sutardja, Albert Wu, Winston Lee, Runzi Chang | 2015-01-13 |
| 8929136 | 8T NVSRAM cell and cell operations | Hsing-Ya Tsao | 2015-01-06 |
| 8923049 | 1T1b and 2T2b flash-based, data-oriented EEPROM design | Hsing-Ya Tsao | 2014-12-30 |
| 8917551 | Flexible 2T-based fuzzy and certain matching arrays | Fu-Chang Hsu | 2014-12-23 |
| 8885388 | Apparatus and method for reforming resistive memory cells | Pantas Sutardja, Albert Wu, Winston Lee, Runzi Chang | 2014-11-11 |
| 8873309 | Apparatus and method for repairing resistive memories and increasing overall read sensitivity of sense amplifiers | Pantas Sutardja, Albert Wu, Runzi Chang, Winston Lee | 2014-10-28 |
| 8837221 | Write bias condition for 2T-string NOR flash cell | Fu-Chang Hsu | 2014-09-16 |
| 8809148 | EEPROM-based, data-oriented combo NVM design | Fu-Chang Hsu | 2014-08-19 |
| 8775719 | NAND-based hybrid NVM design that integrates NAND and NOR in 1-die with parallel interface | Fu-Chang Hsu, Kesheng Wang | 2014-07-08 |
| 8773903 | High speed high density nand-based 2T-NOR flash memory design | Fu-Chang Hsu | 2014-07-08 |
| 8634254 | Single-polycrystalline silicon electrically erasable and programmable memory device of varied gate oxide thickness, using PIP or MIM coupling capacitor for cell size reduction and simultaneous VPP and VNN for write voltage reduction | Fu-Chang Hsu | 2014-01-21 |
| 8634241 | Universal timing waveforms sets to improve random access read and write speed of memories | Fu-Chang Hsu, Hsing-Ya Tsao | 2014-01-21 |
| 8609528 | High-density patterning | Pantas Sutardja, Albert Wu, Winston Lee, Chien-Chuan Wei, Runzi Chang | 2013-12-17 |
| 8582363 | Method and apparatus for management of over-erasure in NAND-based NOR-type flash memory | — | 2013-11-12 |
| 8559232 | DRAM-like NVM memory array and sense amplifier design for high temperature and high endurance operation | Fu-Chang Hsu | 2013-10-15 |
| 8531885 | NAND-based 2T2b NOR flash array with a diode connection to cell's source node for size reduction using the least number of metal layers | Fu-Chang Hsu | 2013-09-10 |
| 8472251 | Single-polycrystalline silicon electrically erasable and programmable nonvolatile memory device | Fu-Chang Hsu | 2013-06-25 |
| 8462553 | Cell array for highly-scalable, byte-alterable, two-transistor FLOTOX EEPROM non-volatile memory | Fu-Chang Hsu | 2013-06-11 |
| 8455923 | Embedded NOR flash memory process with NAND cell and true logic compatible low voltage device | Han-Rei Ma, Fu-Chang Hsu | 2013-06-04 |
| 8355287 | Method and apparatus for operation of a NAND-like dual charge retaining transistor NOR flash memory device | Fu-Chang Hsu | 2013-01-15 |
| 8345481 | NAND based NMOS NOR flash memory cell, a NAND based NMOS NOR flash memory array, and a method of forming a NAND based NMOS NOR flash memory array | Fu-Chang Hsu, Hsing-Ya Tsao | 2013-01-01 |
| 8339195 | Circuits and methods for calibrating offset in an amplifier | Winston Lee | 2012-12-25 |
| 8335108 | Bit line gate transistor structure for a multilevel, dual-sided nonvolatile memory cell NAND flash array | Fu-Chang Hsu | 2012-12-18 |
| 8331150 | Integrated SRAM and FLOTOX EEPROM memory device | Fu-Chang Hsu | 2012-12-11 |
| 8295087 | Row-decoder and select gate decoder structures suitable for flashed-based EEPROM operating below +/− 10v BVDS | Fu-Chang Hsu, Hsing-Ya Tsao | 2012-10-23 |