Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › NAND memory array with BL-hierarchical structure for concurrent all-BL, all-threshold-state program, and alternative-WL program, odd/even read and verify operations

NAND memory array with BL-hierarchical structure for concurrent all-BL, all-threshold-state program, and alternative-WL program, odd/even read and verify operations

US Patent 9659636 · Granted May 23, 2017

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Fabricating memory devices with optimized gate oxide thickness2020
Fabricating memory devices with optimized gate oxide thickness2019
Dual-port memories and input/output circuits for preventing failures correspondi2018
Integrated circuit manufacturing process for aligning threshold voltages of tran2018
Systems and methods for a high performance memory cell structure2017
Self-timed SLC NAND pipeline and concurrent program without verification2017
2D/3D NAND memory array with bit-line hierarchical structure for multi-page conc2017
Partial/full array/block erase for 2D/3D hierarchical NAND2017
Disturb-proof static RAM cells2017
NAND array hiarchical BL structures for multiple-WL and All-BL simultaneous eras2016
Multi-task concurrent/pipeline NAND operations on all planes2016
Resistive random access memory cell structure2016