Issued Patents All Time
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10345371 | Method for parameter extraction of a semiconductor device | Yen-Ying Lin | 2019-07-09 |
| 8691599 | Parameter extraction method for semiconductor device | Kuo-Liang Yeh | 2014-04-08 |
| 7071478 | System and method for passing particles on selected areas on a wafer | Wen-Chin Lin, Denny Tang, Li-Shyue Lai, John Chern, Wan-Yih Lien | 2006-07-04 |
| 6894357 | Gate stack for high performance sub-micron CMOS devices | — | 2005-05-17 |
| 6888063 | Device and method for providing shielding in radio frequency integrated circuits to reduce noise coupling | Wai-Yi Lien, Chung-Long Chang, John Chern | 2005-05-03 |
| 6878964 | Ground-signal-ground pad layout for device tester structure | Wai-Yi Lien | 2005-04-12 |
| 6878583 | Integration method to enhance p+ gate activation | — | 2005-04-12 |
| 6847098 | Non-floating body device with enhanced performance | Horng-Huei Tseng, Chenming Hu, Da-Chi Lin | 2005-01-25 |
| 6835622 | Gate electrode doping method for forming semiconductor integrated circuit microelectronic fabrication with varying effective gate dielectric layer thicknesses | Ling-Yen Yeh, Ih-Chin Chen | 2004-12-28 |
| 6660635 | Pre-LDD wet clean recipe to gain channel length scaling margin beyond sub-0.1 &mgr;m | Wu-Der Wang | 2003-12-09 |
| 6627515 | Method of fabricating a non-floating body device with enhanced performance | Horng-Huei Tseng, Chenming Hu, Da-Chi Lin | 2003-09-30 |
| 6596594 | Method for fabricating field effect transistor (FET) device with asymmetric channel region and asymmetric source and drain regions | — | 2003-07-22 |
| 6596599 | Gate stack for high performance sub-micron CMOS devices | — | 2003-07-22 |
| 6529427 | Test structures for measuring DRAM cell node junction leakage current | — | 2003-03-04 |
| 6528376 | Sacrificial spacer layer method for fabricating field effect transistor (FET) device | — | 2003-03-04 |
| 6352886 | Method of manufacturing floating gate memory with substrate band-to-band tunneling induced hot electron injection | W. J. Tsai | 2002-03-05 |
| 6323077 | Inverse source/drain process using disposable sidewall spacer | — | 2001-11-27 |
| 6103580 | Method to form ultra-shallow buried-channel MOSFETs | — | 2000-08-15 |
| 6009017 | Floating gate memory with substrate band-to-band tunneling induced hot electron injection | W. J. Tsai | 1999-12-28 |
| 5918125 | Process for manufacturing a dual floating gate oxide flash memory cell | Fu-Chia Shone | 1999-06-29 |
| 5243234 | Dual gate LDMOSFET device for reducing on state resistance | Ming-Zen Lin, Kun-Zen Chang | 1993-09-07 |