Issued Patents All Time
Showing 76–97 of 97 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8076199 | Method and device employing polysilicon scaling | Chun Chen, Wenmei Li, Inkuk Kang, Gang Xue, Hyesook Hong | 2011-12-13 |
| 8035153 | Self-aligned patterning method by using non-conformal film and etch for flash memory and other semiconductor applications | Jihwan P. Choi, Calvin T. Gabriel, Fei Wang, Angela T. Hui, Alexander H. Nickel +4 more | 2011-10-11 |
| 7998846 | 3-D integrated circuit system and method | Eunha Kim, Jeremy A. Wahl, Youseok Suh, Kuo-Tung Chang, Yi Ma +2 more | 2011-08-16 |
| 7951704 | Memory device peripheral interconnects and method of manufacturing | Wenmei Li | 2011-05-31 |
| 7943980 | Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductur applications | Kuo-Tung Chang, Tim Thurgate, Youseok Suh, Allison Holbrook | 2011-05-17 |
| 7906395 | Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications | Kuo-Tung Chang, Tim Thurgate, Youseok Suh, Allison Holbrook | 2011-03-15 |
| 7907448 | Scaled down select gates of NAND flash memory cell strings and method of forming same | Youseok Suh, Kuo-Tung Chang | 2011-03-15 |
| 7867899 | Wordline resistance reduction method and structure in an integrated circuit memory device | Jihwan P. Choi, Connie P. Wang, Eunha Kim | 2011-01-11 |
| 7851306 | Method for forming a flash memory device with straight word lines | Hiroyuki Ogawa, Kuo-Tung Chang, Pavel Fastenko, Kazuhiro Mizutani, Zhigang Wang | 2010-12-14 |
| 7829936 | Split charge storage node inner spacer process | Minghao Shen, Wai Lo, Christie Marrian, Chungho Lee, Ning Cheng +2 more | 2010-11-09 |
| 7732276 | Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications | Jihwan P. Choi, Calvin T. Gabriel, Fei Wang, Angela T. Hui, Alexander H. Nickel +4 more | 2010-06-08 |
| 7675104 | Integrated circuit memory system employing silicon rich layers | Amol Joshi, Harpreet Sachar, Youseok Suh, Chih-Yuh Yang, Lovejeet Singh +6 more | 2010-03-09 |
| 7488657 | Method and system for forming straight word lines in a flash memory array | Hiroyuki Ogawa, Kuo-Tung Chang, Pavel Fastenko, Kazuhiro Mizutani, Zhigang Wang | 2009-02-10 |
| 7301193 | Structure and method for low Vss resistance and reduced DIBL in a floating gate memory cell | Timothy Thurgate, Kuo-Tung Chang, Richard Fastow, Angela T. Hui, Kazuhiro Mizutani +4 more | 2007-11-27 |
| 7170130 | Memory cell with reduced DIBL and Vss resistance | Kuo-Tung Chang, Pavel Fastenko, Zhigang Wang | 2007-01-30 |
| 7151028 | Memory cell with plasma-grown oxide spacer for reduced DIBL and Vss resistance and increased reliability | Rinji Sugino, Kuo-Tung Chang, Zhigang Wang, Kazuhiro Mizutani, Pavel Fastenko | 2006-12-19 |
| 7029975 | Method and apparatus for eliminating word line bending by source side implantation | Kuo-Tung Chang, Pavel Fastenko, Kazuhiro Mizutani | 2006-04-18 |
| 6987696 | Method of improving erase voltage distribution for a flash memory array having dummy wordlines | Zhigang Wang, Nian Yang | 2006-01-17 |
| 6974995 | Method and system for forming dual gate structures in a nonvolatile memory using a protective layer | Angela T. Hui, Hiroyuki Kinoshita, Kelwin Ko, Wenmei Li, Yu Sun +2 more | 2005-12-13 |
| 6943401 | Flash memory cell with drain and source formed by diffusion of a dopant from a silicide | — | 2005-09-13 |
| 6927129 | Narrow wide spacer | Yu Sun, Kuo-Tung Chang, Angela T. Hui | 2005-08-09 |
| 6808992 | Method and system for tailoring core and periphery cells in a nonvolatile memory | Kelwin Ko, Angela T. Hui, Hiroyuki Kinoshita, Wenmei Li, Yu Sun +1 more | 2004-10-26 |