Issued Patents All Time
Showing 51–75 of 97 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8874253 | Self-aligned NAND flash select-gate wordlines for spacer double patterning | Tung-Sheng Chen | 2014-10-28 |
| 8835277 | Method to improve charge trap flash memory core cell performance and reliability | Tung-Sheng Chen | 2014-09-16 |
| 8836006 | Integrated circuits with non-volatile memory and methods for manufacture | Kuo-Tung Chang, Chun Chen | 2014-09-16 |
| 8822289 | High voltage gate formation | Chun Chen | 2014-09-02 |
| 8816438 | Process charging protection for split gate charge trapping flash | Chun Chen, Sameer Haddad, Kuo-Tung Chang, Mark T. Ramsbey, Unsoon Kim | 2014-08-26 |
| 8809936 | Memory cell system with multiple nitride layers | Lei Xue, Rinji Sugino, Youseok Suh, Hidehiko Shiraiwa, Meng Ding +1 more | 2014-08-19 |
| 8785275 | Non-volatile FINFET memory device and manufacturing method thereof | Chun Chen | 2014-07-22 |
| 8742496 | Sonos memory cells having non-uniform tunnel oxide and methods for fabricating same | Gang Xue, Wenmei Li, Inkuk Kang | 2014-06-03 |
| 8686492 | Non-volatile FINFET memory device and manufacturing method thereof | Chun Chen | 2014-04-01 |
| 8669597 | Memory device interconnects and method of manufacturing | Connie P. Wang, Wen Yu, Fei Wang | 2014-03-11 |
| 8642441 | Self-aligned STI with single poly for manufacturing a flash memory device | Tim Thurgate, Kuo-Tung Chang, Youseok Suh, Meng Ding, Hidehiko Shiraiwa +5 more | 2014-02-04 |
| 8637918 | Method and device employing polysilicon scaling | Chun Chen, Wenmei Li, Inkuk Kang, Gang Xue, Hyesook Hong | 2014-01-28 |
| 8598646 | Non-volatile FINFET memory array and manufacturing method thereof | Chun Chen | 2013-12-03 |
| 8551858 | Self-aligned SI rich nitride charge trap layer isolation for charge trap flash memory | Angela T. Hui, Shao-Yu Ting, Inkuk Kang, Gang Xue | 2013-10-08 |
| 8487373 | SONOS memory cells having non-uniform tunnel oxide and methods for fabricating same | Gang Xue, Wenmei Li, Inkuk Kang | 2013-07-16 |
| 8461053 | Self-aligned NAND flash select-gate wordlines for spacer double patterning | Tung-Sheng Chen | 2013-06-11 |
| 8441063 | Memory with extended charge trapping layer | Tung-Sheng Chen, Chun Chen | 2013-05-14 |
| 8441041 | Memory device peripheral interconnects | Wenmei Li | 2013-05-14 |
| 8384146 | Methods for forming a memory cell having a top oxide spacer | Angela T. Hui, Gang Xue, Alexander H. Nickel, Kashmir Sahota, Scott A. Bell +2 more | 2013-02-26 |
| 8367537 | Flash memory cell with a flair gate | Meng Ding, Youseok Suh, Kuo-Tung Chang | 2013-02-05 |
| 8349685 | Dual spacer formation in flash memory | Angela T. Hui | 2013-01-08 |
| 8263458 | Process margin engineering in charge trapping field effect transistors | Tung-Sheng Chen | 2012-09-11 |
| 8208296 | Apparatus and method for extended nitride layer in a flash memory | Timothy Thurgate, Kuo-Tung Chang, Youseok Suh | 2012-06-26 |
| 8202779 | Methods for forming a memory cell having a top oxide spacer | Angela T. Hui, Gang Xue, Alexander H. Nickel, Kashmir Sahota, Scott A. Bell +2 more | 2012-06-19 |
| 8143661 | Memory cell system with charge trap | Rinji Sugino, Jayendra D. Bhakta, Takashi Orimoto, Hiroyuki Nansei, Yukio Hayakawa +8 more | 2012-03-27 |