Issued Patents All Time
Showing 25 most recent of 136 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12260159 | System for collaborative hardware RTL logic timing debug in integrated circuit designs | Arun Joseph, Shashidhar Reddy, Sampath Goud Baddam, Anthony Saporito, Matthias Klein | 2025-03-25 |
| 12224316 | Semiconductor device including insulated gate bipolar transistor | Christian Philipp Sandow | 2025-02-11 |
| 12204832 | Logical clock connection in an integrated circuit design | Ali S. El-Zein, Viresh Paruthi, Alvan W. Ng, Benedikt Geukes, Klaus-Dieter Schubert +6 more | 2025-01-21 |
| 12050852 | Signal pre-routing in an integrated circuit design | Ali S. El-Zein, Viresh Paruthi, Stephen G. Shuma, Stephen John Barnfield, Alvan W. Ng +1 more | 2024-07-30 |
| 11775713 | Register transfer level navigation microservices and instrumentation for cloud-native electronic design automation (EDA) platforms | Shiladitya Ghosh, Balaji Pulluru, Pradeep Joy, Arun Joseph | 2023-10-03 |
| 11733295 | Methods and systems for identifying flaws and bugs in integrated circuits, for example, microprocessors | Arun Joseph, Viresh Paruthi, Shiladitya Ghosh, Spandana V. Rachamalla | 2023-08-22 |
| 11663381 | Clock mapping in an integrated circuit design | Stephen G. Shuma, Ali S. El-Zein, Viresh Paruthi, Benedikt Geukes, Klaus-Dieter Schubert +3 more | 2023-05-30 |
| 11645193 | Heterogeneous services for enabling collaborative logic design and debug in aspect oriented hardware designing | Arun Joseph, Anthony Saporito, Matthias Klein, Sampath Goud Baddam, Shashidhar Reddy | 2023-05-09 |
| 11444158 | Semiconductor device including an anode contact region having a varied doping concentration | Christian Philipp Sandow | 2022-09-13 |
| 11296213 | Reverse-conducting igbt having a reduced forward recovery voltage | Christian Philipp Sandow, Matteo Dainese | 2022-04-05 |
| 11004963 | Insulated gate bipolar transistor having first and second field stop zone portions and manufacturing method | Oana Julia Spulber, Matthias Kuenle, Christian Philipp Sandow, Christoph Weiss | 2021-05-11 |
| 10599804 | Pin cloning and subway creation on automatically generated design physical hierarchy | Ali S. El-Zein, Robert J. Shadowen, Alvan W. Ng, Clay Chip Smith | 2020-03-24 |
| 10565338 | Equivalency verification for hierarchical references | Ali S. El-Zein, Mark A. Williams, Robert L. Kanzelman, Viresh Paruthi | 2020-02-18 |
| 10103227 | Method for manufacturing a power semiconductor device | Holger Huesken, Anton Mauder, Hans-Joachim Schulze | 2018-10-16 |
| 9768766 | Electronic switching element and integrated sensor | Stefan Willkofer, Gernot Langguth, Andreas Grassmann | 2017-09-19 |
| 9543398 | Semiconductor switching device including charge storage structure | Johannes Georg Laven, Anton Mauder, Matteo Dainese, Franz Hirler, Christian Jaeger +3 more | 2017-01-10 |
| 8809902 | Power semiconductor diode, IGBT, and method for manufacturing thereof | Holger Huesken, Anton Mauder, Hans-Joachim Schulze | 2014-08-19 |
| 8453080 | Model build in the presence of a non-binding reference | Robert J. Shadowen, Derek E. Williams | 2013-05-28 |
| 8443314 | Abstraction level-preserving conversion of flip-flop-inferred hardware description language (HDL) to instantiated HDL | Ali S. El-Zein, Robert J. Shadowen | 2013-05-14 |
| 8296740 | Annotating system traces with control program information and presenting annotated system traces | Derek E. Williams | 2012-10-23 |
| 8238190 | Clock-gated model transformation for asynchronous testing of logic targeted for free-running, data-gated logic | Yee Ja, Bradley Nelson | 2012-08-07 |
| 8160857 | Selective compilation of a simulation model in view of unavailable higher level signals | Gabor Bobok, Derek E. Williams | 2012-04-17 |
| 8138538 | Interconnect structure for semiconductor devices | Hans-Peter Moll, Gouri Sankar Kar, Martin Popp, Lars Heineck, Peter Lahnor +8 more | 2012-03-20 |
| 8140313 | Techniques for modeling variables in subprograms of hardware description language programs | Gabor Drasny, Ali S. El-Zein, Fadi A. Zaraket | 2012-03-20 |
| 8108199 | Phase events in a simulation model of a digital system | Gabor Bobok, Derek E. Williams | 2012-01-31 |