VJ

Virendra R. Jadhav

IBM: 23 patents #4,681 of 70,183Top 7%
Microsoft: 1 patents #24,826 of 40,388Top 65%
Overall (All Time): #171,842 of 4,157,543Top 5%
24
Patents All Time

Issued Patents All Time

Showing 1–24 of 24 patents

Patent #TitleCo-InventorsDate
11244917 Multilayer pillar for reduced stress interconnect and method of making same Krystyna W. Semkow, Kamalesh K. Srivastava, Brian R. Sundlof 2022-02-08
11171102 Multilayer pillar for reduced stress interconnect and method of making same Krystyna W. Semkow, Kamalesh K. Srivastava, Brian R. Sundlof 2021-11-09
11094657 Multilayer pillar for reduced stress interconnect and method of making same Krystyna W. Semkow, Kamalesh K. Srivastava, Brian R. Sundlof 2021-08-17
10699972 Flat laminate, symmetrical test structures and method of use to gauge white bump sensitivity William E. Bernier, Timothy H. Daubenspeck, Valerie Oberson, David L. Questad 2020-06-30
10403590 Multilayer pillar for reduced stress interconnect and method of making same Krystyna W. Semkow, Kamalesh K. Srivastava, Brian R. Sundlof 2019-09-03
10396051 Multilayer pillar for reduced stress interconnect and method of making same Krystyna W. Semkow, Kamalesh K. Srivastava, Brian R. Sundlof 2019-08-27
10037062 Thermal venting device with pressurized plenum Siddharth Bhopte, Daniel J. Dummer, Andrew Douglas Delano 2018-07-31
9899279 Flat laminate, symmetrical test structures and method of use to gauge white bump sensitivity William E. Bernier, Timothy H. Daubenspeck, Valerie Oberson, David L. Questad 2018-02-20
9640501 Multilayer pillar for reduced stress interconnect and method of making same Krystyna W. Semkow, Kamalesh K. Srivastava, Brian R. Sundlof 2017-05-02
9472520 Multilayer pillar for reduced stress interconnect and method of making same Krystyna W. Semkow, Kamalesh K. Srivastava, Brian R. Sundlof 2016-10-18
9366591 Determining magnitude of compressive loading Paul F. Bodenweber, Steven P. Ostrander, Kamal K. Sikka, Jiantao Zheng, Jeffrey A. Zitz 2016-06-14
9111816 Multilayer pillar for reduced stress interconnect and method of making same Krystyna W. Semkow, Kamalesh K. Srivastava, Brian R. Sundlof 2015-08-18
8957531 Flat laminate, symmetrical test structures and method of use to gauge white bump sensitivity William E. Bernier, Timothy H. Daubenspeck, Valerie Oberson, David L. Questad 2015-02-17
8794079 Determining magnitude of compressive loading Paul F. Bodenweber, Steven P. Ostrander, Kamal K. Sikka, Jiantao Zheng, Jeffrey A. Zitz 2014-08-05
8717043 Determining thermal interface material (TIM) thickness change Paul F. Bodenweber, Kamal K. Sikka, Jiantao Zheng, Jeffrey A. Zitz 2014-05-06
8421217 Achieving mechanical and thermal stability in a multi-chip package Jon A. Casey, John Saunders Corbin, Jr., David Danovitch, Isabelle Depatie, Roger A. Liptak +4 more 2013-04-16
8293587 Multilayer pillar for reduced stress interconnect and method of making same Krystyna W. Semkow, Kamalesh K. Srivastava, Brian R. Sundlof 2012-10-23
8202765 Achieving mechanical and thermal stability in a multi-chip package Jon A. Casey, John Saunders Corbin, Jr., David Danovitch, Isabelle Depatie, Roger A. Liptak +4 more 2012-06-19
7952207 Flip-chip assembly with organic chip carrier having mushroom-plated solder resist opening Jayshree Shah, Kamalesh K. Srivastava 2011-05-31
7875972 Semiconductor device assembly having a stress-relieving buffer layer Kamal K. Sikka, Jiantao Zheng 2011-01-25
7819027 Method and structure for a pull test for controlled collapse chip connections and ball limiting metallurgy Vijayeshwar D. Khanna, David C. Long, David L. Questad 2010-10-26
7812438 Via offsetting to reduce stress under the first level interconnect (FLI) in microelectronics packaging David L. Questad, Kamal K. Sikka, Xiaojin Wei, Jiantao Zheng 2010-10-12
7088008 Electronic package with optimized circuitization pattern David J. Alcoe, William Infantolino 2006-08-08
6703704 Stress reducing stiffener ring David J. Alcoe, Kim J. Blackwell 2004-03-09