Issued Patents All Time
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8557649 | Method for controlling structure height | Rajasekhar Venigalla, Michael V. Aquilino, Michael P. Belyansky, Unoh Kwon, Christopher D. Sheraw +1 more | 2013-10-15 |
| 8435874 | Method of forming openings in a semiconductor device and a semiconductor device fabricated by the method | Scott Warrick, Will Conley, Lionel Riviere-Cazeaux | 2013-05-07 |
| 8187978 | Method of forming openings in a semiconductor device and semiconductor device | Scott Warrick | 2012-05-29 |
| 8101524 | Technique for enhancing the fill capabilities in an electrochemical deposition process by edge rounding of trenches | Kai Frohberg, Matthias Schaller | 2012-01-24 |
| 8043951 | Method of manufacturing a semiconductor device and semiconductor device obtainable therewith | Virginie Beugin | 2011-10-25 |
| 7763547 | Technique for enhancing process flexibility during the formation of vias and trenches in low-k interlayer dielectrics | Thomas Werner, Matthias Schaller | 2010-07-27 |
| 7517816 | Technique for creating different mechanical stress in different channel regions by forming an etch stop layer having differently modified intrinsic stress | Kai Frohberg, Matthias Schaller | 2009-04-14 |
| 7314793 | Technique for controlling mechanical stress in a channel region by spacer removal | Kai Frohberg, Matthias Schaller, Martin Mazur, Roberto Klingler | 2008-01-01 |
| 7309654 | Technique for reducing etch damage during the formation of vias and trenches in interlayer dielectrics | Matthias Schaller, James Werking | 2007-12-18 |
| 7256113 | System for forming a semiconductor device and method thereof | Kay Hellig, Phillip E. Crabtree | 2007-08-14 |
| 7151055 | Technique for forming a gate electrode by using a hard mask | Kay Hellig | 2006-12-19 |
| 7087509 | Method of forming a gate electrode on a semiconductor device and a device incorporating same | William R. Roche, David Wu, Scott Luning | 2006-08-08 |
| 7005380 | Simultaneous formation of device and backside contacts on wafers having a buried insulator layer | Gert Burbach, Christian Zistl | 2006-02-28 |
| 6902870 | Patterning of dielectric with added layers of materials aside from photoresist for enhanced pattern transfer | Kay Hellig | 2005-06-07 |
| 6893956 | Barrier layer for a copper metallization layer including a low-k dielectric | Hartmut Ruelke, Joerg Hohage, Thomas Werner | 2005-05-17 |
| 6828240 | Method of manufacturing multi-level contacts by sizing of contact sizes in integrated circuits | Kay Hellig | 2004-12-07 |
| 6727558 | Channel isolation using dielectric isolation structures | Michael Duane, David Wu, Scott Luning | 2004-04-27 |
| 6699641 | Photosensitive bottom anti-reflective coating | Kay Hellig | 2004-03-02 |
| 6624035 | Method of forming a hard mask for halo implants | Scott Luning, David Wu | 2003-09-23 |
| 6617219 | Semiconductor device and method for lowering miller capacitance by modifying source/drain extensions for high speed microprocessors | Michael Duane, David Wu, Scott Luning | 2003-09-09 |
| 6569606 | Method of reducing photoresist shadowing during angled implants | David Wu, William R. Roche, Scott Luning, Karen L. E. Turnqest | 2003-05-27 |
| 6555472 | Method of producing a semiconductor device using feature trimming | — | 2003-04-29 |
| 6482726 | Control trimming of hard mask for sub-100 nanometer transistor gate | David Wu, Scott Luning | 2002-11-19 |