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Arranging through silicon vias in IC layout |
Donald R. Dean, Jr., Peter J. Lindgren, Edmund J. Sprogis, Anthony K. Stamper |
2012-03-13 |
| 7714366 |
CMOS transistor with a polysilicon gate electrode having varying grain size |
Arne Ballantine, Kevin K. Chan, Jeffrey D. Gilbert, Kevin M. Houlihan, James J. Quinlivan +3 more |
2010-05-11 |
| 6893948 |
Method of reducing polysilicon depletion in a polysilicon gate electrode by depositing polysilicon of varying grain size |
Arne Ballantine, Kevin K. Chan, Jeffrey D. Gilbert, Kevin M. Houlihan, James J. Quinlivan +3 more |
2005-05-17 |
| 6853032 |
Structure and method for formation of a blocked silicide resistor |
Arne Ballantine, Donna K. Johnson |
2005-02-08 |
| 6670263 |
Method of reducing polysilicon depletion in a polysilicon gate electrode by depositing polysilicon of varying grain size |
Arne Ballantine, Kevin K. Chan, Jeffrey D. Gilbert, Kevin M. Houlihan, James J. Quinlivan +3 more |
2003-12-30 |
| 6660664 |
Structure and method for formation of a blocked silicide resistor |
James W. Adkisson, Arne Ballantine, Matthew D. Gallagher, Peter J. Geiss, Jeffrey D. Gilbert +6 more |
2003-12-09 |
| 6509265 |
Process for manufacturing a contact barrier |
Patrick W. DeHaven, Anthony G. Domenicucci, Lynne M. Gignac, Prabhat Tiwari, Yun-Yu Wang +2 more |
2003-01-21 |
| 6348419 |
Modification of the wet characteristics of deposited layers and in-line control |
Frank Grellner, Paul C. Jamison, David C. Mosher, Emmanuel Batt |
2002-02-19 |
| 6250803 |
Method for temperature measurement using dopant segregation into titanium silicide |
Arne Ballantine |
2001-06-26 |
| 6235597 |
Semiconductor structure having reduced silicide resistance between closely spaced gates and method of fabrication |
— |
2001-05-22 |
| 6187679 |
Low temperature formation of low resistivity titanium silicide |
Cyril Cabral, Jr., Lawrence A. Clevenger, Francois M. d'Heurle, James M. E. Harper, Randy W. Mann +3 more |
2001-02-13 |
| 6180521 |
Process for manufacturing a contact barrier |
Patrick W. DeHaven, Anthony G. Domenicucci, Lynne M. Gignac, Prabhat Tiwari, Yun-Yu Wang +2 more |
2001-01-30 |
| 6180456 |
Triple polysilicon embedded NVRAM cell and method thereof |
Chung H. Lam, Jame Spiros Nakos, Christa R. Willets |
2001-01-30 |
| 6069040 |
Fabricating a floating gate with field enhancement feature self-aligned to a groove |
Robert K. Leidy |
2000-05-30 |
| 6060358 |
Damascene NVRAM cell and method of manufacture |
John A. Bracchitta, Jeffrey B. Johnson |
2000-05-09 |
| 5828131 |
Low temperature formation of low resistivity titanium silicide |
Cyril Cabral, Jr., Lawrence A. Clevenger, Francois M. d'Heurle, James M. E. Harper, Randy W. Mann +3 more |
1998-10-27 |
| 5510295 |
Method for lowering the phase transformation temperature of a metal silicide |
Cyril Cabral, Jr., Lawrence A. Clevenger, Francois M. d'Heurle, James M. E. Harper, Randy W. Mann +1 more |
1996-04-23 |
| 4983544 |
Silicide bridge contact process |
Nicky C. Lu, Brian J. Machesney, Rick L. Mohler, Chung-Yu Ting, Stephen D. Warley |
1991-01-08 |
