Issued Patents All Time
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8756554 | Identifying parasitic diode(s) in an integrated circuit physical design | Edward W. Seibert, Lijiang Wang | 2014-06-17 |
| 8191030 | Identifying parasitic diode(s) in an integrated circuit physical design | Edward W. Seibert, Lijiang Wang | 2012-05-29 |
| 7941780 | Intersect area based ground rule for semiconductor design | Albrik Avanessian, Henry A. Bonges, III, Dureseti Chidambarrao, Stephen E. Greco, Tina Wagner | 2011-05-10 |
| 7849426 | Mechanism for detection and compensation of NBTI induced threshold degradation | Kenneth J. Goodnow, Stephen G. Shuma, Oscar C. Strohacker, Mark S. Styduhar, Peter A. Twombly +1 more | 2010-12-07 |
| 7696811 | Methods and circuits to reduce threshold voltage tolerance and skew in multi-threshold voltage applications | Corey K. Barrows, Stephen G. Shuma, Douglas W. Stout, Oscar C. Strohacker, Mark S. Styduhar +1 more | 2010-04-13 |
| 7671666 | Methods to reduce threshold voltage tolerance and skew in multi-threshold voltage applications | Corey K. Barrows, Stephen G. Shuma, Douglas W. Stout, Oscar C. Strohacker, Mark S. Styduhar +1 more | 2010-03-02 |
| 7619398 | Programmable on-chip sense line | Corey K. Barrows, Douglas W. Stout, Peter A. Twombly | 2009-11-17 |
| 7504847 | Mechanism for detection and compensation of NBTI induced threshold degradation | Kenneth J. Goodnow, Stephen G. Shuma, Oscar C. Strohacker, Mark S. Styduhar, Peter A. Twembly +1 more | 2009-03-17 |
| 7490303 | Identifying parasitic diode(s) in an integrated circuit physical design | Edward W. Seibert, Lijiang Wang | 2009-02-10 |
| 7459958 | Circuits to reduce threshold voltage tolerance and skew in multi-threshold voltage applications | Corey K. Barrows, Stephen G. Shuma, Douglas W. Stout, Oscar C. Strohacker, Mark S. Styduhar +1 more | 2008-12-02 |
| 7397228 | Programmable on-chip sense line | Corey K. Barrows, Douglas W. Sinut, Peter A. Twombly | 2008-07-08 |
| 7146596 | Integrated circuit chip having a ringed wiring layer interposed between a contact layer and a wiring grid | Thomas R. Bednar, Timothy W. Budell, Patrick H. Buffet, Alain Caron, James V. Crain, Jr. +2 more | 2006-12-05 |
| 7076749 | Method and system for improving integrated circuit manufacturing productivity | Daniel N. Maynard, Gustavo E. Tellez, Lijiang Wang, Peter S. Wissell | 2006-07-11 |
| 6908841 | Support structures for wirebond regions of contact pads over low modulus materials | Lloyd Burrell, Henry A. Nye, III, Hans-Joachim Barth, Emmanuel F. Crabbe, David F. Anderson +1 more | 2005-06-21 |
| 6577156 | Method and apparatus for initializing an integrated circuit using compressed data from a remote fusebox | Darren L. Anand, John E. Barth, Jr., John A. Fifield, Pamela S. Gillis, Peter O. Jakobsen +4 more | 2003-06-10 |
| 6426890 | Shared ground SRAM cell | Eric Jasinski | 2002-07-30 |
| 6308302 | Semiconductor wiring technique for reducing electromigration | David J. Hathaway, William J. Livingstone, Daniel Joseph Mainiero, Joseph Leonard Metz, Jeannie Therese Harrigan Panner | 2001-10-23 |
| 5737580 | Wiring design tool improvement for avoiding electromigration by determining optimal wire widths | David J. Hathaway, William J. Livingstone, Daniel Joseph Mainiero, Joseph Leonard Metz, Jeannie Therese Harrigan Panner | 1998-04-07 |
| 5369595 | Method of combining gate array and standard cell circuits on a common semiconductor chip | Elliot L. Gould, Lance A. McAllister, Ronald A. Piro, Guy R. Richardson, Deborah A. Wellburn | 1994-11-29 |
| 5051917 | Method of combining gate array and standard cell circuits on a common semiconductor chip | Elliot L. Gould, Lance A. McAllister, Ronald A. Piro, Guy R. Richardson, Deborah A. Wellburn | 1991-09-24 |
| 4786613 | Method of combining gate array and standard cell circuits on a common semiconductor chip | Elliot L. Gould, Lance A. McAllister, Ronald A. Piro, Guy R. Richardson, Deborah A. Wellburn | 1988-11-22 |