BK

Brion Keller

CS Cadence Design Systems: 11 patents #99 of 2,263Top 5%
IBM: 8 patents #13,150 of 70,183Top 20%
Overall (All Time): #255,528 of 4,157,543Top 7%
18
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
9864004 System and method for diagnosing failure locations in electronic circuits Sameer Chakravarthy Chillarige, Joseph Michael Swenton, Sharjinder Singh, Anil Malik 2018-01-09
9404969 Method and apparatus for efficient hierarchical chip testing and diagnostics with support for partially bad dies Steven M. Douskey, Mary P. Kusko 2016-08-02
8887019 Method and system for providing efficient on-product clock generation for domains compatible with compression Karishna Chakravadhanula, Ramana Malneedi 2014-11-11
8732632 Method and apparatus for automated extraction of a design for test boundary model from embedded IP cores for hierarchical and three-dimensional interconnect test Pradeep Nagaraj, Richard Schoonover, Vivek Chickermane 2014-05-20
8468404 Method and system for reducing switching activity during scan-load operations Vivek Chickermane, Karishna Chakravadhanula 2013-06-18
8296703 Fault modeling for state retention logic Krishna Vijaya Chakravadhanula, Steven Lee Gregor, Vivek Chickermane 2012-10-23
7693676 Low power scan test for integrated circuits Vivek Chickermane, Sandeep Bhatia 2010-04-06
7523370 Channel masking during integrated circuit testing 2009-04-21
7487420 System and method for performing logic failure diagnosis using multiple input signature register output streams 2009-02-03
7435990 Arrangement for testing semiconductor chips while incorporated on a semiconductor wafer Bernd Koenemann, David E. Lackey, Donald L. Wheater 2008-10-14
7381986 Arrangement for testing semiconductor chips while incorporated on a semiconductor wafer Bernd K. F. Koenermann, David E. Lackey, Donald L. Wheater 2008-06-03
7103816 Method and system for reducing test data volume in the testing of logic products Frank Distler, Leonard O. Farnsworth, III, Andrew Ferko, Bernd Koenemann, Donald L. Wheater 2006-09-05
6986090 Method for reducing switching activity during a scan operation with limited impact on the test coverage of an integrated circuit David J. Hathaway 2006-01-10
6804803 Method for testing integrated logic circuits Carl Barnhart, Robert W. Bassett, David E. Lackey, Mark R. Taylor, Donald L. Wheater 2004-10-12
6782501 System for reducing test data volume in the testing of logic products Frank Distler, L. Farnsworth, Andrew Ferko, Bernd Koenemann 2004-08-24
6708305 Deterministic random LBIST L. Farnsworth, Bernd Koenemann, Timothy J. Koprowski, Thomas J. Snethen, Donald L. Wheater 2004-03-16
6611933 Real-time decoder for scan test patterns Bernd Koenemann, Carl Barnhart 2003-08-26
5546408 Hierarchical pattern faults for describing logic circuit failure mechanisms 1996-08-13