KC

Karishna Chakravadhanula

CS Cadence Design Systems: 2 patents #781 of 2,263Top 35%
📍 Vestal, NY: #239 of 481 inventorsTop 50%
🗺 New York: #48,759 of 115,490 inventorsTop 45%
Overall (All Time): #2,061,399 of 4,157,543Top 50%
2
Patents All Time

Issued Patents All Time

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
8887019 Method and system for providing efficient on-product clock generation for domains compatible with compression Brion Keller, Ramana Malneedi 2014-11-11
8468404 Method and system for reducing switching activity during scan-load operations Vivek Chickermane, Brion Keller 2013-06-18