AP

Ashok S. Prabhu

IN Invensas: 23 patents #17 of 142Top 15%
NS National Semiconductor: 22 patents #55 of 2,238Top 3%
TI Texas Instruments: 9 patents #1,613 of 12,488Top 15%
AT Adeia Semiconductor Bonding Technologies: 1 patents #30 of 46Top 70%
📍 San Jose, CA: #807 of 32,062 inventorsTop 3%
🗺 California: #6,736 of 386,348 inventorsTop 2%
Overall (All Time): #45,277 of 4,157,543Top 2%
55
Patents All Time

Issued Patents All Time

Showing 26–50 of 55 patents

Patent #TitleCo-InventorsDate
9911718 ‘RDL-First’ packaged microelectronic device for a package-on-package device Rajesh Katkar 2018-03-06
9871019 Flipped die stack assemblies with leadframe interconnects Rajesh Katkar, Liang Wang, Cyprian Emeka Uzoh 2018-01-16
9825002 Flipped die stack Rajesh Katkar, Reynaldo Co, Scott McGrath, Sangil Lee, Liang Wang +1 more 2017-11-21
9812402 Wire bond wires for interference shielding Abiola Awujoola, Zhuowen Sun, Wael Zohni, Willmar Subido 2017-11-07
9761554 Ball bonding metal wire bond wires to metal pads Willmar Subido, Reynaldo Co, Wael Zohni 2017-09-12
9666513 Wafer-level flipped die stacks with leadframes or metal foil interconnects Rajesh Katkar, Sean MORAN 2017-05-30
9490195 Wafer-level flipped die stacks with leadframes or metal foil interconnects Rajesh Katkar, Sean MORAN 2016-11-08
9490222 Wire bond wires for interference shielding Abiola Awujoola, Zhuowen Sun, Wael Zohni, Willmar Subido 2016-11-08
8679896 DC/DC converter power module package incorporating a stacked controller and construction methodology Rajeev Joshi, Jaime A. Bayan 2014-03-25
8674418 Method and apparatus for achieving galvanic isolation in package having integral isolation medium Anindya Poddar, Vijaylaxmi Khanolkar, Peter Johnson 2014-03-18
8283760 Lead frame interconnect scheme with high power density Ken Pham, Anindya Poddar 2012-10-09
7795126 Electrical die contact structure and fabrication method Sadanand R. Patil, Shaw Wei Lee, Alexander H. Owens 2010-09-14
7615407 Methods and systems for packaging integrated circuits with integrated passive components Anindya Poddar 2009-11-10
7491625 Gang flipping for IC packaging Jaime A. Bayan, Nghia Thuc Tu, Anindya Poddar 2009-02-17
7340181 Electrical die contact structure and fabrication method Sadanand R. Patil, Shaw Wei Lee, Alexander H. Owens 2008-03-04
7259460 Wire bonding on thinned portions of a lead-frame configured for use in a micro-array integrated circuit package Jamie A. BAYAN, Chan Peng Yeen, Hasfiza Ramley, Santhiran Nadarajah 2007-08-21
7205095 Apparatus and method for packaging image sensing semiconductor chips Shaw Wei Lee 2007-04-17
7186588 Method of fabricating a micro-array integrated circuit package Jaime A. Bayan, Santhiran Nadarajah, Chan Chee Ling, Hasfiza Ramley, Chan Peng Yeen 2007-03-06
7102209 Substrate for use in semiconductor manufacturing and method of making same Jaime A. Bayan, Fred Drummond 2006-09-05
7087986 Solder pad configuration for use in a micro-array integrated circuit package Jaime A. Bayan, Shaw Wei Lee 2006-08-08
7067354 Electrical die contact structure and fabrication method 2006-06-27
7064419 Die attach region for use in a micro-array integrated circuit package Jaime A. Bayan, Chan Chee Ling, Lye Meng Kong, Santhiran Nadarajah 2006-06-20
6933597 Spacer with passive components for use in multi-chip modules Anindya Poddar 2005-08-23
6791072 Method and apparatus for forming curved image sensor module 2004-09-14
6781244 Electrical die contact structure and fabrication method 2004-08-24