Issued Patents All Time
Showing 26–47 of 47 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9898330 | Compacted context state management | Atul Khare, Leena K. Puthiyedath, Asit K. Mallick, Jim Coke, Gilbert Neiger +2 more | 2018-02-20 |
| 9891695 | Flushing and restoring core memory content to external memory | Alexander Gendler, Ariel Berkovits, Nadav Shulman, Sameer Desai, Shani Rehana +2 more | 2018-02-13 |
| 9760158 | Forcing a processor into a low power state | Eliezer Weissmann, Yoni Aizik, Doron Rajwan, Nir Rosenzweig, Efraim Rotem +11 more | 2017-09-12 |
| 9727345 | Method for booting a heterogeneous system and presenting a symmetric core view | Eliezer Weissmann, Rinat Rappoport, Hisham Shafi, Oron Lenz, Jason W. Brandt +19 more | 2017-08-08 |
| 9720730 | Providing an asymmetric multicore processor system transparently to an operating system | Boris Ginzburg, Ilya Osadchiy, Ronny Ronen, Eliezer Weissmann, Alon Naveh +13 more | 2017-08-01 |
| 9684541 | Method and apparatus for determining thread execution parallelism | Eliezer Weissmann, Arik Gihon, Efraim Rotem, Paul S. Diefenbaugh, Eric C. Samson +2 more | 2017-06-20 |
| 9660799 | Changing the clock frequency of a computing device | Alexander Gendler, Ernest Knoll, Ofer Nathan, Krishnakanth V. Sistla, Ariel Sabba +4 more | 2017-05-23 |
| 9519324 | Local power gate (LPG) interfaces for power-aware operations | Ron Gabor, Robert Valentine, Alex Gerber, Zeev Sperber | 2016-12-13 |
| 9501132 | Instruction and logic for store broadcast and power management | Stanislav Shwartsman, Gal Ofir, Yulia Kurolap | 2016-11-22 |
| 9448879 | Apparatus and method for implement a multi-level memory hierarchy | Theodros Yigzaw, Oded Lempel, Hisham Shafi, Geeyarpuram N. Santhanakrishnan, Jose A. Vargas +6 more | 2016-09-20 |
| 9396056 | Conditional memory fault assist suppression | Zeev Sperber, Robert Valentine, Offer Levy, Gal Ofir | 2016-07-19 |
| 9361101 | Extension of CPU context-state management for micro-architecture state | Efraim Rotem, Eliezer Weissmann, Boris Ginzburg, Alon Naveh | 2016-06-07 |
| 9348594 | Core switching acceleration in asymmetric multiprocessor system | Koichi Yamada, Boris Ginzburg, Wei Li, Ronny Ronen, Esfir Natanzon +4 more | 2016-05-24 |
| 9250901 | Execution context swap between heterogeneous functional hardware units | Inder M. Sodhi, Marc Torrant, Zeev Offen, Ashish V. Choubal, Jason W. Brandt | 2016-02-02 |
| 9152205 | Mechanism for facilitating faster suspend/resume operations in computing systems | Ohad Falik, Eliezer Weissmann, Alon Naveh, Nadav Shulman, Robert E. Gough +3 more | 2015-10-06 |
| 9058201 | Managing and tracking thread access to operating system extended features using map-tables containing location references and thread identifiers | James B. Crossland, Boris Ginzburg, Eliezer Weissmann | 2015-06-16 |
| 8935514 | Optimizing performance of instructions based on sequence detection or information associated with the instructions | Ohad Falik, Lihu Rappoport, Ron Gabor, Yulia Kurolap | 2015-01-13 |
| 8909988 | Recoverable parity and residue error | Zeev Sperber, Ofer Levy, Ron Gabor | 2014-12-09 |
| 8677163 | Context state management for processor feature sets | Don A. Van Dyke, Ittai Anati, Baiju V. Patel, Will Deutsch, Rajesh R. Sha +7 more | 2014-03-18 |
| 8631261 | Context state management for processor feature sets | Don A. Van Dyke, Ittai Anati, Baiju V. Patel, Will Deutsch, Rajesh Shah +7 more | 2014-01-14 |
| 8543796 | Optimizing performance of instructions based on sequence detection or information associated with the instructions | Ohad Falik, Lihu Rappoport, Ron Gabor, Yulia Kurolap | 2013-09-24 |
| 7558946 | Breaking a lock situation in a processor without detection of the lock situation using a multi-level approach | Avi Mendelson, Julius Mandelblat | 2009-07-07 |