Issued Patents All Time
Showing 301–325 of 340 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7479431 | Strained NMOS transistor featuring deep carbon doped regions and raised donor doped source and drain | Michael L. Hattendorf, Jack Hwang, Andrew N. Westmeyer | 2009-01-20 |
| 7473947 | Process for ultra-thin body SOI devices that incorporate EPI silicon tips and article made thereby | Brian S. Doyle, Jack T. Kavalieros, Robert S. Chau | 2009-01-06 |
| 7436035 | Method of fabricating a field effect transistor structure with abrupt source/drain junctions | Robert S. Chau, Patrick Morrow, Chia-Hong Jan, Paul Packan | 2008-10-14 |
| 7427775 | Fabricating strained channel epitaxial source/drain transistors | Justin K. Brask, Andrew N. Westmeyer, Boyan Boyanov, Nick Lindert | 2008-09-23 |
| 7422971 | Process for ultra-thin body SOI devices that incorporate EPI silicon tips and article made thereby | Brian S. Doyle, Jack T. Kavalieros, Robert S. Chau | 2008-09-09 |
| 7402872 | Method for forming an integrated circuit | Glenn A. Glass, Andrew N. Westmeyer, Michael L. Hattendorf, Tahir Ghani | 2008-07-22 |
| 7391087 | MOS transistor structure and method of fabrication | Robert S. Chau, Patrick Morrow | 2008-06-24 |
| 7364976 | Selective etch for patterning a semiconductor film deposited non-selectively | Willy Rachmady | 2008-04-29 |
| 7358547 | Selective deposition to improve selectivity and structures formed thereby | Nayanee Gupta, Chris Auth, Glenn A. Glass | 2008-04-15 |
| 7338873 | Method of fabricating a field effect transistor structure with abrupt source/drain junctions | Robert S. Chau, Patrick Morrow, Chia-Hong Jan, Paul Packan | 2008-03-04 |
| 7274055 | Method for improving transistor performance through reducing the salicide interface resistance | Boyan Boyanov, Glenn A. Glass, Thomas Hoffmann | 2007-09-25 |
| 7226842 | Fabricating strained channel epitaxial source/drain transistors | Justin K. Brask, Andrew N. Westmeyer, Boyan Boyanov, Nick Lindert | 2007-06-05 |
| 7223679 | Transistor gate electrode having conductor material layer | Boyan Boyanov, Suman Datta, Brian S. Doyle, Been-Yih Jin, Shaofeng Yu +1 more | 2007-05-29 |
| 7202514 | Self aligned compact bipolar junction transistor layout and method of making same | Shahriar Ahmed, Mark Bohr, Stephen Chambers, Richard Green | 2007-04-10 |
| 7195985 | CMOS transistor junction regions formed by a CVD etching and deposition sequence | Glenn A. Glass, Andrew N. Westmeyer, Michael L. Hattendorf, Jeffrey R. Wank | 2007-03-27 |
| 7129139 | Methods for selective deposition to improve selectivity | Nayanee Gupta, Chris Auth, Glenn A. Glass | 2006-10-31 |
| 7064042 | Self aligned compact bipolar junction transistor layout, and method of making same | Shahriar Ahmed, Mark Bohr, Stephen Chambers, Richard Green | 2006-06-20 |
| 7060576 | Epitaxially deposited source/drain | Nick Lindert, Justin K. Brask | 2006-06-13 |
| 7005359 | Bipolar junction transistor with improved extrinsic base region and method of fabrication | Shahriar Ahmed, Ravindra Soman, Mark Bohr | 2006-02-28 |
| 6974733 | Double-gate transistor with enhanced carrier mobility | Boyan Boyanov, Brian S. Doyle, Jack T. Kavalieros, Robert S. Chau | 2005-12-13 |
| 6972228 | Method of forming an element of a microelectronic circuit | Brian S. Doyle, Robert S. Chau | 2005-12-06 |
| 6952040 | Transistor structure and method of fabrication | Robert S. Chau, Jack T. Kavalieros, Brian Roberds, Brian S. Doyle | 2005-10-04 |
| 6949482 | Method for improving transistor performance through reducing the salicide interface resistance | Boyan Boyanov, Glenn A. Glass, Thomas Hoffmann | 2005-09-27 |
| 6933589 | Method of making a semiconductor transistor | Boyan Boyanov, Ravindra Soman, Robert S. Chau | 2005-08-23 |
| 6927140 | Method for fabricating a bipolar transistor base | Ravindra Soman | 2005-08-09 |