TL

Thomas E. Lombardi

IBM: 32 patents #3,111 of 70,183Top 5%
Globalfoundries: 3 patents #1,029 of 4,424Top 25%
📍 Poughkeepsie, NY: #108 of 1,613 inventorsTop 7%
🗺 New York: #3,219 of 115,490 inventorsTop 3%
Overall (All Time): #97,674 of 4,157,543Top 3%
35
Patents All Time

Issued Patents All Time

Showing 26–35 of 35 patents

Patent #TitleCo-InventorsDate
8129230 Underfill method and chip package Michael A. Gaynes, Rajneesh Kumar, Steve Ostrander 2012-03-06
6762119 Method of preventing solder wetting in an optical device using diffusion of Cr Sudipta K. Ray, Mitchell S. Cohen, Lester W. Herron, Mario J. Interrante, Subhash L. Shinde 2004-07-13
6528352 Use of conductive adhesive to form temporary electrical connections for use in TCA (temporary chip attach) applications Raymond A. Jackson, John U. Knickerbocker, Amy B. Ostrander 2003-03-04
6518674 Temporary attach article and method for temporary attach of devices to a substrate Mario J. Interrante, Frank L. Pompeo, William E. Sablinski 2003-02-11
6376054 Surface metallization structure for multiple chip test and burn-in Scott I. Langenthal, Richard F. Indyk, John U. Knickerbocker, Srinivasa S. N. Reddy, Richard A. Shelleman +2 more 2002-04-23
6303400 Temporary attach article and method for temporary attach of devices to a substrate Mario J. Interrante, Frank L. Pompeo, William E. Sablinski 2001-10-16
5795217 Stressed burnisher Mark J. LaPlante, David C. Long, Anton Nenadic, Alan Piciacchio 1998-08-18
5643818 Removal of residues from metallic insert used in manufacture of multi-layer ceramic substrate with cavity for microelectronic chip Krishna G. Sachdev, Vincent P. Peterson 1997-07-01
5489465 Edge seal technology for low dielectric/porous substrate processing Govindarajan Natarajan, Takeshi Takamori, Katharine G. Frase, Robert A. Rita 1996-02-06
5480503 Process for producing circuitized layers and multilayer ceramic sub-laminates and composites thereof Jon A. Casey, David B. Goland, Dinesh Gupta, Lester W. Herron, James N. Humenik +3 more 1996-01-02