Issued Patents All Time
Showing 101–115 of 115 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7456115 | Method for forming semiconductor devices having reduced gate edge leakage current | Anthony I. Chou | 2008-11-25 |
| 7446062 | Device having dual etch stop liner and reformed silicide layer and related methods | Dureseti Chidambarrao, Ying Li, Rajeev Malik | 2008-11-04 |
| 7446395 | Device having dual etch stop liner and protective layer | Dureseti Chidambarrao, Ying Li, Rajeev Malik | 2008-11-04 |
| 7348635 | Device having enhanced stress state and related methods | Dureseti Chidambarrao, Ying Li, Rajeev Malik, Haining Yang, Huilong Zhu | 2008-03-25 |
| 7329923 | High-performance CMOS devices on hybrid crystal oriented substrates | Bruce B. Doris, Kathryn Guarini, Meikei Ieong, Kern Rim, Jeffrey W. Sleight +1 more | 2008-02-12 |
| 7306983 | Method for forming dual etch stop liner and protective layer in a semiconductor device | Dureseti Chidambarrao, Ying Li, Rajeev Malik | 2007-12-11 |
| 7274072 | Hybrid bulk-SOI 6T-SRAM cell for improved cell stability and performance | Leland Chang, Norman J. Rohrer, Jeffrey W. Sleight | 2007-09-25 |
| 7227204 | Structure for improved diode ideality | Edward P. Maciejewski, Sherry A. Womack, Christopher D. Sheraw | 2007-06-05 |
| 7202187 | Method of forming sidewall spacer using dual-frequency plasma enhanced CVD | Ravikumar Ramachandran, James T. Kelliher, Jeffrey W. Sleight | 2007-04-10 |
| 7189644 | CMOS device integration for low external resistance | Patricia A. O'Neil | 2007-03-13 |
| 7091128 | Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETs | Atul Ajmera, Andres Bryant, Percy V. Gilbert, Michael A. Gribelyuk, Edward P. Maciejewski +1 more | 2006-08-15 |
| 7071072 | Forming shallow trench isolation without the use of CMP | Renee T. Mo | 2006-07-04 |
| 7001844 | Material for contact etch layer to enhance device performance | Ashima B. Chakravarti, Victor Chan, Judson R. Holt, Satya N. Chakravarti | 2006-02-21 |
| 6991979 | Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETs | Atul Ajmera, Andres Bryant, Percy V. Gilbert, Michael A. Gribelyuk, Edward P. Maciejewski +1 more | 2006-01-31 |
| 6825102 | Method of improving the quality of defective semiconductor material | Stephen W. Bedell, Keith E. Fogel, Devendra K. Sadana | 2004-11-30 |