Issued Patents All Time
Showing 276–300 of 360 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10141441 | Vertical transistor with back bias and reduced parasitic capacitance | Kangguo Cheng, Xin Miao, Chen Zhang | 2018-11-27 |
| 10134595 | High aspect ratio gates | Kangguo Cheng, Sivananda K. Kanakasabapathy | 2018-11-20 |
| 10134859 | Transistor with asymmetric spacers | Zhenxing Bi, Kangguo Cheng, Heng Wu | 2018-11-20 |
| 10128004 | High temperature strength, corrosion resistant, accident tolerant nuclear fuel assembly grid | Edward J. Lahoda | 2018-11-13 |
| 10128235 | Asymmetrical vertical transistor | Zhenxing Bi, Kangguo Cheng, Juntao Li | 2018-11-13 |
| 10128238 | Integrated circuit having oxidized gate cut region and method to fabricate same | Kangguo Cheng, Andrew M. Greene | 2018-11-13 |
| 10115728 | Laser spike annealing for solid phase epitaxy and low contact resistance in an SRAM with a shared PFET and NFET trench | Zuoguang Liu, Gen Tsutsui, Heng Wu | 2018-10-30 |
| 10103063 | Forming a hybrid channel nanosheet semiconductor structure | Kangguo Cheng | 2018-10-16 |
| 10103243 | Unipolar spacer formation for finFETS | Kangguo Cheng, Jie Yang | 2018-10-16 |
| 10096524 | Semiconductor fin patterning techniques to achieve uniform fin profiles for fin field effect transistors | Zhenxing Bi, Kangguo Cheng, Juntao Li | 2018-10-09 |
| 10096695 | Closely packed vertical transistors with reduced contact resistance | Zhenxing Bi, Kangguo Cheng, Juntao Li | 2018-10-09 |
| 10090412 | Vertical transistor with back bias and reduced parasitic capacitance | Kangguo Cheng, Xin Miao, Chen Zhang | 2018-10-02 |
| 10084094 | Wrapped source/drain contacts with enhanced area | Kangguo Cheng, Zuoguang Liu, Heng Wu | 2018-09-25 |
| 10079229 | Resistor fins | Zhenxing Bi, Kangguo Cheng, Juntao Li | 2018-09-18 |
| 10079287 | Gate cut device fabrication with extended height gates | Kangguo Cheng, Andrew M. Greene, John R. Sporre | 2018-09-18 |
| 10068980 | Vertical fin with a gate structure having a modified gate geometry | Kangguo Cheng | 2018-09-04 |
| 10068898 | On-chip MIM capacitor | Kangguo Cheng | 2018-09-04 |
| 10068807 | Uniform shallow trench isolation | Kangguo Cheng, Junli Wang, Chen Zhang | 2018-09-04 |
| 10068804 | Methods, apparatus and system for providing adjustable fin height for a FinFET device | Ruilong Xie, Chun Wing Yeung | 2018-09-04 |
| 10062458 | SiC matrix fuel cladding tube with spark plasma sintered end plugs | Edward J. Lahoda, Lars Hallstadius, Joon Hyung Choi, Shinichi Higuichi, Fumihisa Kano | 2018-08-28 |
| 10060018 | Kinetically applied gradated Zr-Al-C ceramic or Ti-Al-C ceramic or amorphous or semi-amorphous stainless steel with nuclear grade zirconium alloy metal structure | Edward J. Lahoda, Jason P. Mazzoccoli | 2018-08-28 |
| 10056289 | Fabrication of vertical transport fin field effect transistors with a self-aligned separator and an isolation region with an air gap | Kangguo Cheng, Zuoguang Liu, Sebastian Naczas, Heng Wu | 2018-08-21 |
| 10043900 | Vertical transport Fin field effect transistors on a substrate with varying effective gate lengths | Zhenxing Bi, Kangguo Cheng, Juntao Li | 2018-08-07 |
| 10017421 | Method for preparing active calcium silicate | Junmin Sun, Chenghai Wang, Zhanjun Zhang, Yang Chen, Zhijun Gao +1 more | 2018-07-10 |
| 10008601 | Self-aligned gate cut with polysilicon liner oxidation | Kangguo Cheng | 2018-06-26 |