Issued Patents All Time
Showing 51–75 of 97 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7144787 | Methods to improve the SiGe heterojunction bipolar device performance | Gregory G. Freeman, Marwan H. Khater, Rajendran Krishnasamy, Kathryn T. Schonenberg | 2006-12-05 |
| 7091563 | Method and structure for improved MOSFETs using poly/silicide gate height control | Dureseti Chidambarrao | 2006-08-15 |
| 7060539 | Method of manufacture of FinFET devices with T-shaped fins and devices manufactured thereby | Dureseti Chidambarrao | 2006-06-13 |
| 7056773 | Backgated FinFET having different oxide thicknesses | Andres Bryant, Hussein I. Hanafi, Edward J. Nowak | 2006-06-06 |
| 7041538 | Method of manufacturing a disposable reversed spacer process for high performance recessed channel CMOS | Meikei Ieong, Thomas S. Kanarsky, Victor Ku | 2006-05-09 |
| 7041600 | Methods of planarization | Bruce B. Doris, David V. Horak, Fen F. Jamin | 2006-05-09 |
| 7037770 | Method of manufacturing strained dislocation-free channels for CMOS | Dureseti Chidambarrao | 2006-05-02 |
| 7037818 | Apparatus and method for staircase raised source/drain structure | Xinlin Wang, Huilong Zhu | 2006-05-02 |
| 7026247 | Nanocircuit and self-correcting etching method for fabricating same | Oleg Gluschenkov | 2006-04-11 |
| 6989322 | Method of forming ultra-thin silicidation-stop extensions in mosfet devices | Oleg Gluschenkov, Cyril Cabral, Jr., Christian Lavoie | 2006-01-24 |
| 6977194 | Structure and method to improve channel mobility by gate electrode stress modification | Michael P. Belyansky, Dureseti Chidambarrao, Bruce B. Doris, Oleg Gluschenkov | 2005-12-20 |
| 6974981 | Isolation structures for imposing stress patterns | Dureseti Chidambarrao, Bruce B. Doris, Jack A. Mandelman | 2005-12-13 |
| 6933577 | High performance FET with laterally thin extension | Cyril Cabral, Jr., Oleg Gluschenkov | 2005-08-23 |
| 6914303 | Ultra thin channel MOSFET | Bruce B. Doris, Thomas S. Kanarsky, Ying Zhang, Huilong Zhu, Meikei Ieong | 2005-07-05 |
| 6911384 | Gate structure with independently tailored vertical doping profile | Bruce B. Doris, Oleg Gluschenkov, Jack A. Mandelman, Carl Radens | 2005-06-28 |
| 6890808 | Method and structure for improved MOSFETs using poly/silicide gate height control | Dureseti Chidambarrao | 2005-05-10 |
| 6887751 | MOSFET performance improvement using deformation in SOI structure | Dureseti Chidambarrao | 2005-05-03 |
| 6878978 | CMOS performance enhancement using localized voids and extended defects | Dureseti Chidambarrao, Suryanarayan G. Hegde | 2005-04-12 |
| 6878582 | Low-GIDL MOSFET structure and method for fabrication | Bruce B. Doris, Oleg Gluschenkov, Jack A. Mandelman, Carl Radens | 2005-04-12 |
| 6873010 | High performance logic and high density embedded dram with borderless contact and antispacer | Dureseti Chidambarrao, Bruce B. Doris, Oleg Gluschenkov, Rajarao Jammy, Jack A. Mandelman | 2005-03-29 |
| 6872641 | Strained silicon on relaxed sige film with uniform misfit dislocation density | Dureseti Chidambarrao | 2005-03-29 |
| 6869866 | Silicide proximity structures for CMOS device performance improvements | Dureseti Chidambarrao, Rajesh Rengarajan, An Steegen | 2005-03-22 |
| 6858488 | CMOS performance enhancement using localized voids and extended defects | Dureseti Chidambarrao, Suryanarayan G. Hegde | 2005-02-22 |
| 6841826 | Low-GIDL MOSFET structure and method for fabrication | Bruce B. Doris, Oleg Gluschenkov, Jack A. Mandelman, Carl Radens | 2005-01-11 |
| 6833569 | Self-aligned planar double-gate process by amorphization | Bruce B. Doris, Suryanarayan G. Hegde, Meikei Ieong, Erin C. Jones | 2004-12-21 |