Issued Patents All Time
Showing 26–50 of 97 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7495291 | Strained dislocation-free channels for CMOS and method of manufacture | Dureseti Chidambarrao | 2009-02-24 |
| 7476946 | Backgated FinFET having different oxide thicknesses | Andres Bryant, Hussein I. Hanafi, Edward J. Nowak | 2009-01-13 |
| 7476914 | Methods to improve the SiGe heterojunction bipolar device performance | Gregory G. Freeman, Marwan H. Khater, Rajendran Krishnasamy, Kathryn T. Schonenberg | 2009-01-13 |
| 7453123 | Self-aligned planar double-gate transistor structure | Bruce B. Doris, Kathryn Guarini, Suryanarayan G. Hegde, Meikei Ieong, Erin C. Jones | 2008-11-18 |
| 7410846 | Method for reduced N+ diffusion in strained Si on SiGe substrate | Dureseti Chidambarrao | 2008-08-12 |
| 7402870 | Ultra shallow junction formation by epitaxial interface limited diffusion | Huajie Chen, Oleg Gluschenkov, Werner Rausch | 2008-07-22 |
| 7397081 | Sidewall semiconductor transistors | Huilong Zhu, Lawrence A. Clevenger, Kaushik A. Kumar, Carl Radens, Dureseti Chidambarrao | 2008-07-08 |
| 7374987 | Stress inducing spacers | Dureseti Chidambarrao, Bruce B. Doris, Jack A. Mandelman, Xavier Baie | 2008-05-20 |
| 7361973 | Embedded stressed nitride liners for CMOS performance improvement | Dureseti Chidambarrao | 2008-04-22 |
| 7345329 | Method for reduced N+ diffusion in strained Si on SiGe substrate | Dureseti Chidambarrao | 2008-03-18 |
| 7312134 | Dual stressed SOI substrates | Dureseti Chidambarrao, Bruce B. Doris, Oleg Gluschenkov, Huilong Zhu | 2007-12-25 |
| 7303949 | High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture | Huajie Chen, Dureseti Chidambarrao | 2007-12-04 |
| 7297601 | Method for reduced N+ diffusion in strained Si on SiGe substrate | Dureseti Chidambarrao | 2007-11-20 |
| 7271446 | Ultra-thin channel device with raised source and drain and solid source extension doping | Bruce B. Doris | 2007-09-18 |
| 7262087 | Dual stressed SOI substrates | Dureseti Chidambarrao, Bruce B. Doris, Oleg Gluschenkov, Huilong Zhu | 2007-08-28 |
| 7247534 | Silicon device on Si:C-OI and SGOI and method of manufacture | Dureseti Chidambarrao, Oleg Gluschenkov | 2007-07-24 |
| 7223994 | Strained Si on multiple materials for bulk or SOI substrates | Dureseti Chidambarrao, Oleg Gluschenkov, Huilong Zhu | 2007-05-29 |
| 7224021 | MOSFET with high angle sidewall gate and contacts for reduced miller capacitance | Dureseti Chidambarrao, Lawrence A. Clevenger, Kaushik A. Kumar, Huilong Zhu | 2007-05-29 |
| 7211490 | Ultra thin channel MOSFET | Bruce B. Doris, Thomas S. Kanarsky, Ying Zhang, Huilong Zhu, Meikei Ieong | 2007-05-01 |
| 7205185 | Self-aligned planar double-gate process by self-aligned oxidation | Bruce B. Doris, Kathryn Guarini, Suryanarayan G. Hegde, Meikei Ieong, Erin C. Jones | 2007-04-17 |
| 7198995 | Strained finFETs and method of manufacture | Dureseti Chidambarrao, Oleg Gluschenkov | 2007-04-03 |
| 7187042 | Backgated FinFET having different oxide thicknesses | Andres Bryant, Hussein I. Hanafi, Edward J. Nowak | 2007-03-06 |
| 7176116 | High performance FET with laterally thin extension | Cyril Cabral, Jr., Oleg Gluschenkov | 2007-02-13 |
| 7170772 | Apparatus and method for dynamic control of double gate devices | Alper Buyuktosunoglu | 2007-01-30 |
| 7144767 | NFETs using gate induced stress modulation | Dureseti Chidambarrao, Oleg Gluschenkov | 2006-12-05 |