Issued Patents All Time
Showing 76–97 of 97 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6825529 | Stress inducing spacers | Dureseti Chidambarrao, Bruce B. Doris, Jack A. Mandelman, Xavier Baie | 2004-11-30 |
| 6812105 | Ultra-thin channel device with raised source and drain and solid source extension doping | Bruce B. Doris | 2004-11-02 |
| 6806534 | Damascene method for improved MOS transistor | Bruce B. Doris, Oleg Gluschenkov, Jack A. Mandelman, Carl Radens | 2004-10-19 |
| 6803315 | Method for blocking implants from the gate of an electronic device via planarizing films | Bruce B. Doris | 2004-10-12 |
| 6780694 | MOS transistor | Bruce B. Doris, Jack A. Mandelman, Carl Radens | 2004-08-24 |
| 6764883 | Amorphous and polycrystalline silicon nanolaminate | Oleg Gluschenkov, Michael Belyanksy, Bruce B. Doris | 2004-07-20 |
| 6709926 | High performance logic and high density embedded dram with borderless contact and antispacer | Dureseti Chidambarrao, Bruce B. Doris, Oleg Gluschenkov, Rajarao Jammy, Jack A. Mandelman | 2004-03-23 |
| 6686637 | Gate structure with independently tailored vertical doping profile | Bruce B. Doris, Oleg Gluschenkov, Jack A. Mandelman, Carl Radens | 2004-02-03 |
| 6677646 | Method and structure of a disposable reversed spacer process for high performance recessed channel CMOS | Meikei Ieong, Thomas S. Kanarsky, Victor Ku | 2004-01-13 |
| 6667197 | Method for differential oxidation rate reduction for n-type and p-type materials | Oleg Gluschenkov, Bruce B. Doris | 2003-12-23 |
| 6657244 | Structure and method to reduce silicon substrate consumption and improve gate sheet resistance during silicide formation | Bruce B. Doris, Robert J. Purtell | 2003-12-02 |
| 6645867 | Structure and method to preserve STI during etching | Bruce B. Doris | 2003-11-11 |
| 6642147 | Method of making thermally stable planarizing films | Bruce B. Doris, Michael P. Belyansky | 2003-11-04 |
| 6586289 | Anti-spacer structure for improved gate activation | Bruce B. Doris | 2003-07-01 |
| 6569781 | Method of forming an ultra-thin oxide layer on a silicon substrate by implantation of nitrogen through a sacrificial layer and subsequent annealing prior to oxide formation | Richard D. Kaplan, Mukesh V. Khare, Suryanarayan G. Hegde | 2003-05-27 |
| 6566210 | Method of improving gate activation by employing atomic oxygen enhanced oxidation | Atul Ajmera, Bruce B. Doris, Oleg Gluschenkov | 2003-05-20 |
| 6562713 | Method of protecting semiconductor areas while exposing a gate | Michael P. Belyansky, Bruce B. Doris, Hussein I. Hanafi | 2003-05-13 |
| 6531365 | Anti-spacer structure for self-aligned independent gate implantation | Bruce B. Doris, Peter Smeys, Isabel Yang | 2003-03-11 |
| 6514843 | Method of enhanced oxidation of MOS transistor gate corners | Oleg Gluschenkov, Suryanarayan G. Hegde, Richard D. Kaplan, Mukesh V. Khare | 2003-02-04 |
| 6509221 | Method for forming high performance CMOS devices with elevated sidewall spacers | Bruce B. Doris, Oleg Gluschenkov | 2003-01-21 |
| 6387782 | Process of forming an ultra-shallow junction dopant layer having a peak concentration within a dielectric layer | Hiroyuki Akatsu, Suryanarayan G. Hegde, Yujun Li, Rajesh Rengarajan, Paul A. Ronsheim | 2002-05-14 |
| 6329704 | Ultra-shallow junction dopant layer having a peak concentration within a dielectric layer | Hiroyuki Akatsu, Suryanarayan G. Hegde, Yujun Li, Rajesh Rengarajan, Paul A. Ronsheim | 2001-12-11 |