Issued Patents All Time
Showing 51–75 of 255 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10658180 | EUV pattern transfer with ion implantation and reduced impact of resist residue | Yann Mignot, Yongan Xu | 2020-05-19 |
| 10651308 | Self aligned top extension formation for vertical transistors | Sanjay C. Mehta, Shogo Mochizuki, Alexander Reznicek | 2020-05-12 |
| 10651089 | Low thermal budget top source and drain region formation for vertical transistors | Alexander Reznicek, Shogo Mochizuki | 2020-05-12 |
| 10643006 | Semiconductor chip including integrated security circuit | Kangguo Cheng | 2020-05-05 |
| 10622379 | Structure and method to form defect free high-mobility semiconductor fins on insulator | Veeraraghavan S. Basker, Shogo Mochizuki, Alexander Reznicek | 2020-04-14 |
| 10586769 | Contact formation in semiconductor devices | Jiseok Kim, Zuoguang Liu, Shogo Mochizuki, Hiroaki Niimi | 2020-03-10 |
| 10553439 | Multiple nanosecond laser pulse anneal processes and resultant semiconductor structure | Aritra Dasgupta | 2020-02-04 |
| 10551742 | Tunable adhesion of EUV photoresist on oxide surface | Yongan Xu, Jing Guo, Ekmini Anuja De Silva | 2020-02-04 |
| 10529828 | Method of forming vertical transistor having dual bottom spacers | Sanjay C. Mehta, Shogo Mochizuki, Alexander Reznicek | 2020-01-07 |
| 10510617 | CMOS VFET contacts with trench solid and liquid phase epitaxy | Zuoguang Liu, Shogo Mochizuki, Hiroaki Niimi, Tenko Yamashita | 2019-12-17 |
| 10388789 | Reducing series resistance between source and/or drain regions and a channel region | Mona A. Ebrish | 2019-08-20 |
| 10381442 | Low resistance source drain contact formation | Zuoguang Liu, Shogo Mochizuki, Hiroaki Niimi, Chun-Chen Yeh | 2019-08-13 |
| 10374088 | Low parasitic capacitance and resistance finFET device | Ahmet S. Ozcan | 2019-08-06 |
| 10361306 | High acceptor level doping in silicon germanium | Mona A. Ebrish, Shogo Mochizuki, Alexander Reznicek | 2019-07-23 |
| 10347581 | Contact formation in semiconductor devices | Jiseok Kim, Zuoguang Liu, Shogo Mochizuki, Hiroaki Niimi | 2019-07-09 |
| 10319855 | Reducing series resistance between source and/or drain regions and a channel region | Mona A. Ebrish | 2019-06-11 |
| 10319722 | Contact formation in semiconductor devices | Zuoguang Liu, Hiroaki Niimi, Joseph S. Washington, Tenko Yamashita | 2019-06-11 |
| 10297614 | Gate top spacer for FinFET | Veeraraghavan S. Basker, Shogo Mochizuki, Alexander Reznicek | 2019-05-21 |
| 10269652 | Vertical transistor top epitaxy source/drain and contact structure | Sanjay C. Mehta, Shogo Mochizuki, Alexander Reznicek | 2019-04-23 |
| 10262904 | Vertical transistor top epitaxy source/drain and contact structure | Sanjay C. Mehta, Shogo Mochizuki, Alexander Reznicek | 2019-04-16 |
| 10249502 | Low resistance source drain contact formation with trench metastable alloys and laser annealing | Zuoguang Liu, Shogo Mochizuki, Hiroaki Niimi, Tenko Yamashita, Chun-Chen Yeh | 2019-04-02 |
| 10236360 | Method of forming vertical transistor having dual bottom spacers | Sanjay C. Mehta, Shogo Mochizuki, Alexander Reznicek | 2019-03-19 |
| 10211207 | Low resistance source/drain contacts for complementary metal oxide semiconductor (CMOS) devices | Praneet Adusumilli, Dechao Guo, Zuoguang Liu, Rajasekhar Venigalla, Tenko Yamashita | 2019-02-19 |
| 10170620 | Substantially defect free relaxed heterogeneous semiconductor fins on bulk substrates | Veeraraghavan S. Basker, Shogo Mochizuki, Alexander Reznicek | 2019-01-01 |
| 10141308 | Low resistance source/drain contacts for complementary metal oxide semiconductor (CMOS) devices | Praneet Adusumilli, Dechao Guo, Zuoguang Liu, Rajasekhar Venigalla, Tenko Yamashita | 2018-11-27 |