JF

Julien Frougier

IBM: 146 patents #302 of 70,183Top 1%
Globalfoundries: 42 patents #54 of 4,424Top 2%
GU Globalfoundries U.S.: 17 patents #32 of 665Top 5%
TE Tessera: 2 patents #162 of 271Top 60%
AS Adeia Semiconductor Solutions: 1 patents #22 of 57Top 40%
📍 Albany, NY: #1 of 790 inventorsTop 1%
🗺 New York: #134 of 115,490 inventorsTop 1%
Overall (All Time): #3,041 of 4,157,543Top 1%
209
Patents All Time

Issued Patents All Time

Showing 151–175 of 209 patents

Patent #TitleCo-InventorsDate
10903315 Formation of dielectric layer as etch-stop for source and drain epitaxy disconnection Nicolas Loubet, Robin Hsin Kuo Chao, Ruilong Xie 2021-01-26
10886378 Method of forming air-gap spacers and gate contact over active region and the resulting device Ruilong Xie, Chanro Park, Kangguo Cheng 2021-01-05
10872962 Steep-switch field effect transistor with integrated bi-stable resistive system Nicolas Loubet, Ruilong Xie, Daniel Chanemougame, Ali Razavieh, Kangguo Cheng 2020-12-22
10840146 Structures and SRAM bit cells with a buried cross-couple interconnect Bipul C. Paul, Ruilong Xie 2020-11-17
10833191 Integrating nanosheet transistors, on-chip embedded memory, and extended-gate transistors on the same substrate Ruilong Xie, Kangguo Cheng, Juntao Li 2020-11-10
10832954 Forming a reliable wrap-around contact without source/drain sacrificial regions Kangguo Cheng, Ruilong Xie 2020-11-10
10818803 Fin-type field-effect transistors including a two-dimensional material Ali Razavieh 2020-10-27
10818792 Nanosheet field-effect transistors formed with sacrificial spacers Ruilong Xie, Daniel Chanemougame 2020-10-27
10818674 Structures and SRAM bit cells integrating complementary field-effect transistors Randy W. Mann, Bipul C. Paul, Ruilong Xie 2020-10-27
10804398 Method of forming wrap-around-contact and the resulting device Ruilong Xie 2020-10-13
10790376 Contact structures Ruilong Xie, Chanro Park, Kangguo Cheng, Andre P. Labonte 2020-09-29
10784171 Vertically stacked complementary-FET device with independent gate control Ruilong Xie, Puneet Harischandra Suvarna 2020-09-22
10770566 Unique gate cap and gate cap spacer structures for devices on integrated circuit products Ruilong Xie, Chanro Park, Kangguo Cheng 2020-09-08
10756203 Sub-thermal switching slope vertical field effect transistor with dual-gate feedback loop mechanism Ruilong Xie, Steven R. Bentley, Kangguo Cheng, Nicolas Loubet, Pietro Montanini 2020-08-25
10741639 Formation of dielectric layer as etch-stop for source and drain epitaxy disconnection Nicolas Loubet, Robin Hsin Kuo Chao, Ruilong Xie 2020-08-11
10741675 Sub-thermal switching slope vertical field effect transistor with dual-gate feedback loop mechanism Ruilong Xie, Steven R. Bentley, Kangguo Cheng, Nicolas Loubet, Pietro Montanini 2020-08-11
10734525 Gate-all-around transistor with spacer support and methods of forming same Ruilong Xie, Christopher M. Prindle, Nigel G. Cave 2020-08-04
10714567 Nanosheet field-effect transistor with substrate isolation Ruilong Xie 2020-07-14
10692991 Gate-all-around field effect transistors with air-gap inner spacers and methods Daniel Chanemougame, Ruilong Xie 2020-06-23
10679894 Airgap spacers formed in conjunction with a late gate cut Ruilong Xie, Chanro Park, Kangguo Cheng 2020-06-09
10665692 Non-self aligned gate contacts formed over the active region of a transistor Ruilong Xie, Chanro Park, Kangguo Cheng 2020-05-26
10665669 Insulative structure with diffusion break integral with isolation layer and methods to form same Ruilong Xie 2020-05-26
10651291 Inner spacer formation in a nanosheet field-effect transistor Ruilong Xie 2020-05-12
10644157 Fin-type field effect transistors with uniform channel lengths and below-channel isolation on bulk semiconductor substrates and methods Ruilong Xie, Andreas Knorr, Srikanth B. Samavedam 2020-05-05
10629516 Hybrid dual damascene structures with enlarged contacts Daniel Chanemougame, Ruilong Xie 2020-04-21