Issued Patents All Time
Showing 26–50 of 60 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9401698 | Transforming a phase-locked-loop generated chip clock signal to a local clock signal | Yuen H. Chan, Rolf Sautter, Tobias Werner | 2016-07-26 |
| 9098659 | Advanced array local clock buffer base block circuit | Osama Dengler, Thomas Froehnel, Rolf Sautter | 2015-08-04 |
| 8942052 | Complementary metal-oxide-semiconductor (CMOS) min/max voltage circuit for switching between multiple voltages | William V. Huott, Michael Kugel, Rolf Sautter, Dieter Wendel | 2015-01-27 |
| 8493812 | Boost circuit for generating an adjustable boost voltage | Osama Dengler, Alexander Fritsch, Wolfgang Penth | 2013-07-23 |
| 8237481 | Low power programmable clock delay generator with integrated decode function | Yuen H. Chan, Rolf Sautter, Michael Ju Hyeok Lee | 2012-08-07 |
| 7936198 | Progamable control clock circuit for arrays | Rolf Sautter, Michael Ju Hyeok Lee, Yuen H. Chan | 2011-05-03 |
| 7921388 | Wordline booster design structure and method of operating a wordine booster circuit | Sebastian Ehrenreich, Otto A. Torreiter | 2011-04-05 |
| 7844871 | Test interface for memory elements | Uwe Brandt, Stefan Buettner, Werner Juchmes | 2010-11-30 |
| 7844799 | Method and system for pipeline reduction | Jens Leenstra, Antje Mueller, Dieter Wendel | 2010-11-30 |
| 7813163 | Single-ended read and differential write scheme | Otto Wagner, Sebastian Ehrenreich, Rolf Sautter | 2010-10-12 |
| 7808856 | Method to reduce leakage of a SRAM-array | Sebastian Ehrenreich, Dieter Wendel | 2010-10-05 |
| 7760541 | Functional float mode screen to test for leakage defects on SRAM bitlines | Chad A. Adams | 2010-07-20 |
| 7755408 | Redundancy in signal distribution trees | Sebastian Ehrenreich, Juergen Koehl | 2010-07-13 |
| 7710796 | Level shifter for boosting wordline voltage and memory cell performance | Scott Raymond Cottier, Sang Hoo Dhong, Rajiv V. Joshi, Osamu Takahashi | 2010-05-04 |
| 7675794 | Design structure for improving performance of SRAM cells, SRAM cell, SRAM array, and write circuit | Derick G. Behrends, Sebastian Ehrenreich, Otto Wagner | 2010-03-09 |
| 7636254 | Wordline booster circuit and method of operating a wordline booster circuit | Sebastian Ehrenreich, Otto A. Torreiter | 2009-12-22 |
| 7626851 | Method to improve performance of SRAM cells, SRAM cell, SRAM array, and write circuit | Derick G. Behrends, Sebastian Ehrenreich, Otto Wagner | 2009-12-01 |
| 7401312 | Automatic method for routing and designing an LSI | Ulrich Krauch, Tobias Werner, Alexander Woerner | 2008-07-15 |
| 7388773 | Random access memory with a plurality of symmetrical memory cells | Chad A. Adams, Torsten Mahuke, Oto Wagner | 2008-06-17 |
| 7336115 | Redundancy in signal distribution trees | Sebastian Ehrenreich, Juergen Koehl | 2008-02-26 |
| 7295481 | Power saving by disabling cyclic bitline precharge | Rolf Sautter, Christian Schweizer, Klaus Thumm | 2007-11-13 |
| 7289370 | Methods and apparatus for accessing memory | Chad A. Adams, Anthony Gus Aipperspach, Otto Wagner | 2007-10-30 |
| 7194399 | Automatic check for cyclic operating conditions for SOI circuit simulation | Karl-Eugen Kroell, Helmut Schettler | 2007-03-20 |
| 7092310 | Memory array with multiple read ports | Martin Eckert, Dieter Wendel | 2006-08-15 |
| 6977863 | Device and method for decoding an address word into word-line signals | Stefan Buettner, Jens Leenstra, Christian Schweizer | 2005-12-20 |