Issued Patents All Time
Showing 51–72 of 72 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9342307 | Allocation of counters from a pool of counters to track mappings of logical registers to physical registers for mapper based instruction executions | Brian D. Barrick, John W. Ward, III | 2016-05-17 |
| 9075600 | Program status word dependency handling in an out of order microprocessor design | Brian D. Barrick, Michael Billeci, Fadi Y. Busaba, Bruce C. Giamei, David A. Schroter | 2015-07-07 |
| 9069546 | Allocation of counters from a pool of counters to track mappings of logical registers to physical registers for mapper based instruction executions | Brian D. Barrick, John W. Ward, III | 2015-06-30 |
| 8751747 | Management of cache replacement status in cache memory | Robert J. Sonnelitter, III, Brian R. Prasky | 2014-06-10 |
| 8667258 | High performance cache translation look-aside buffer (TLB) lookups using multiple page size prediction | Brian R. Prasky, James J. Bonanno, Aaron Tsai, Joshua M. Weinberg | 2014-03-04 |
| 8661230 | Allocation of counters from a pool of counters to track mappings of logical registers to physical registers for mapper based instruction executions | Brian D. Barrick, John W. Ward, III | 2014-02-25 |
| 8521992 | Predicting and avoiding operand-store-compare hazards in out-of-order microprocessors | Khary J. Alexander, Brian W. Curran, Jonathan T. Hsieh, Christian Jacobi, James R. Mitchell +2 more | 2013-08-27 |
| 8468325 | Predicting and avoiding operand-store-compare hazards in out-of-order microprocessors | Khary J. Alexander, Brian W. Curran, Jonathan T. Hsieh, Christian Jacobi, James R. Mitchell +2 more | 2013-06-18 |
| 8453124 | Collecting computer processor instrumentation data | Jane H. Bartik, Michael Billeci, David S. Hutton, Christian Jacobi, Jang-Soo Lee +3 more | 2013-05-28 |
| 8433855 | Serializing translation lookaside buffer access around address translation parameter modification | Lisa C. Heller, Chung-Lung K. Shum | 2013-04-30 |
| 8082467 | Triggering workaround capabilities based on events active in a processor pipeline | Fadi Y. Busaba, David A. Schroter, Eric M. Schwarz, Brian W. Thompto, Wesley J. Ward, III | 2011-12-20 |
| 8015362 | Method and system for handling cache coherency for self-modifying code | Christian Jacobi, Barry W. Krumm, Chung-Lung K. Shum, Aaron Tsai | 2011-09-06 |
| 7793086 | Link stack misprediction resolution | — | 2010-09-07 |
| 7769984 | Dual-issuance of microprocessor instructions using dual dependency matrices | Brian D. Barrick, Lee Evan Eisen, John W. Ward, III | 2010-08-03 |
| 7674538 | Apparatus and method for high efficiency operation of a high temperature fuel cell system | Malcolm James Grieve, John MacBain, Kaushik Rajashekara | 2010-03-09 |
| 7645532 | Solid-oxide fuel cell system having an upstream reformate combustor | Amanda M. Weiss, Subhasish Mukerjee, Karl J. Haltiner, Jr. | 2010-01-12 |
| 7549095 | Error detection enhancement in a microprocessor through the use of a second dependency matrix | Lee Evan Eisen, Brian W. Thompto, John W. Ward, III | 2009-06-16 |
| 7306871 | Hybrid power generating system combining a fuel cell and a gas turbine | Malcolm James Grieve, John MacBain, Kaushik Rajashekara, Brett W. Buck, Daniel D. Richey | 2007-12-11 |
| 7254678 | Enhanced STCX design to improve subsequent load efficiency | Juan Jose Arevalo, Balaram Sinharoy, Shih-Hsiung S. Tung | 2007-08-07 |
| 7120784 | Thread-specific branch prediction by logically splitting branch history tables and predicted target address cache in a simultaneous multithreading processing environment | Scott Bruce Frommer, David S. Levitan, Balaram Sinharoy | 2006-10-10 |
| 7039768 | Cache predictor for simultaneous multi-threaded processor system supporting multiple transactions | David S. Levitan, Balaram Sinharoy | 2006-05-02 |
| 7032097 | Zero cycle penalty in selecting instructions in prefetch buffer in the event of a miss in the instruction cache | David S. Levitan, Balaram Sinharoy, William J. Starke | 2006-04-18 |