Issued Patents All Time
Showing 26–50 of 78 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9851738 | Programmable voltage reference | Bal S. Sandhu, Robert Campbell Aitken | 2017-12-26 |
| 9805777 | Sense amplifier | Bal S. Sandhu, Cezary Pietrzyk, Robert Campbell Aitken | 2017-10-31 |
| 9786370 | CES-based latching circuits | Robert Campbell Aitken, Vikas Chandra, Bal S. Sandhu, Shidhartha Das, John Philip Biggs +2 more | 2017-10-10 |
| 9748943 | Programmable current for correlated electron switch | Bal S. Sandhu, Robert Campbell Aitken | 2017-08-29 |
| 9741410 | Memory circuitry using write assist voltage boost | Andy Wangkun Chen, Yew Keong Chong, Gus Yeung, Bo Zheng | 2017-08-22 |
| 9620200 | Retention voltages for integrated circuits | Sanjay Mangal, Gus Yeung, Martin Jay Kinkade, Rahul Mathur, Bal S. Sandhu | 2017-04-11 |
| 9514814 | Memory write driver, method and system | Bal S. Sandhu, Cezary Pietrzyk | 2016-12-06 |
| 9374072 | Post fabrication tuning of an integrated circuit | Betina Hold, Brian Tracy Cline | 2016-06-21 |
| 9142266 | Memory circuitry using write assist voltage boost | Andy Wangkun Chen, Yew Keong Chong, Gus Yeung, Bo Zheng | 2015-09-22 |
| 8296526 | Shared memory having multiple access configurations | Kari Ann O'Brien, Joern Soersensen, Matthew B. Rutledge, Paul William Hollis | 2012-10-23 |
| 7466607 | Memory access system and method using de-coupled read and write circuits | Paul William Hollis, Matthew B. Rutledge | 2008-12-16 |
| 7440312 | Memory write timing system | Paul William Hollis | 2008-10-21 |
| 6915385 | Apparatus for unaligned cache reads and methods therefor | Terry Lee Leasure, Robert A. Ross, Gus Yeung | 2005-07-05 |
| 6737888 | Method for skipping a latch in timing-sensitive dynamic circuits of a multi-clocked system with unspecific underlap requirement | Donald George Mikan, Jr., Jose Angel Paredes, Gus Yeung | 2004-05-18 |
| 6640293 | Apparatus and method of utilizing Alias Hit signals to detect errors within the real address tag arrays | Jose Angel Paredes, Bruce Joseph Ronchetti, Binta M. Patel | 2003-10-28 |
| 6629215 | Multiple port memory apparatus | Juergen Pille, Rolf Sautter, Dieter Wendel | 2003-09-30 |
| 6604173 | System for controlling access to external cache memories of differing size | Hoichi Cheong, Dwain A. Hicks, Peichun Peter Liu | 2003-08-05 |
| 6477635 | Data processing system including load/store unit having a real address tag array and method for correcting effective address aliasing | James Allan Kahle, Jose Angel Paredes, Larry Edward Thatcher | 2002-11-05 |
| 6412051 | System and method for controlling a memory array in an information handling system | Brian R. Konigsburg, John Stephen Muhich | 2002-06-25 |
| 6353558 | Method and apparatus for writing to memory cells | Jose Angel Paredes | 2002-03-05 |
| 6243776 | Selectable differential or single-ended mode bus | Robert J. Reese, Gus Yeung | 2001-06-05 |
| 6219296 | Multiport memory cell having a reduced number of write wordlines | Dieter Wendel, Friedrich-Christian Wernicke | 2001-04-17 |
| 6195280 | Memory system having a unidirectional bus and method for communicating therewith | Younes Lotfi, Robert A. Ross, Gus Yeung | 2001-02-27 |
| 6191620 | Sense amplifier/comparator circuit and data comparison method | Terry Lee Leasure, Younes Lotfi, Robert A. Ross, Gus Yeung | 2001-02-20 |
| 6157216 | Circuit driver on SOI for merged logic and memory circuits | Donald George Mikan, Jr., Binta M. Patel, Gus Yeung | 2000-12-05 |