Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11569800 | Detection and correction of single event upset (SEU) in integrated circuit | — | 2023-01-31 |
| 11283431 | Detection and correction of single event upset (SEU) in integrated circuit | — | 2022-03-22 |
| 11195674 | Radiation-hardened break before make circuit | Thomas R. Richardson, James E. Colley | 2021-12-07 |
| 10074493 | Radiation-hardened break before make circuit | Thomas R. Richardson, James E. Colley | 2018-09-11 |
| 6195280 | Memory system having a unidirectional bus and method for communicating therewith | George McNeil Lattimore, Robert A. Ross, Gus Yeung | 2001-02-27 |
| 6191620 | Sense amplifier/comparator circuit and data comparison method | George McNeil Lattimore, Terry Lee Leasure, Robert A. Ross, Gus Yeung | 2001-02-20 |
| 6081458 | Memory system having a unidirectional bus and method for communicating therewith | George McNeil Lattimore, Robert A. Ross, Gus Yeung | 2000-06-27 |
| 5894432 | CMOS memory cell with improved read port | — | 1999-04-13 |
| 5892725 | Memory in a data processing system having uneven cell grouping on bitlines and method therefor | George McNeil Lattimore, Robert A. Ross, Gus Yeung | 1999-04-06 |
| 5828239 | Sense amplifier circuit with minimized clock skew effect | — | 1998-10-27 |
| 5764589 | Array row and column decoder apparatus and method | — | 1998-06-09 |
| 5717342 | Output buffer incorporating shared intermediate nodes | John D. Porter | 1998-02-10 |
| 5654645 | Buffer with controlled hysteresis | — | 1997-08-05 |