Issued Patents All Time
Showing 51–75 of 78 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6144609 | Multiport memory cell having a reduced number of write wordlines | Dieter Wendel, Friedrich-Christian Wernicke | 2000-11-07 |
| 6134164 | Sensing circuit for a memory cell array | Gus Yeung | 2000-10-17 |
| 6108255 | Conditional restore for RAM based on feedback from a RAM cell to precharge circuitry | Michael Kevin Ciraula, Gus Yeung | 2000-08-22 |
| 6081458 | Memory system having a unidirectional bus and method for communicating therewith | Younes Lotfi, Robert A. Ross, Gus Yeung | 2000-06-27 |
| 6064616 | Conditional restore for SRAM | Michael Kevin Ciraula, Gus Yeung | 2000-05-16 |
| 6058065 | Memory in a data processing system having improved performance and method therefor | Terry Lee Leasure, Robert A. Ross, Gus Yeung | 2000-05-02 |
| 6046930 | Memory array and method for writing data to memory | Michael Kevin Ciraula, Terry Lee Leasure, Gus Yeung | 2000-04-04 |
| 6025741 | Conditional restore for execution unit | Michael Kevin Ciraula, Gus Yeung | 2000-02-15 |
| 6021512 | Data processing system having memory sub-array redundancy and method therefor | Robert P. Masleid, John Stephen Muhich | 2000-02-01 |
| 6002626 | Method and apparatus for memory cell array boost amplifier | Robert A. Ross, Gus Yeung | 1999-12-14 |
| 5982692 | Bit line boost amplifier | Robert A. Ross, Gus Yeung | 1999-11-09 |
| 5963486 | Bit switch circuit and bit line selection method | Gus Yeung, Robert A. Ross | 1999-10-05 |
| 5956286 | Data processing system and method for implementing a multi-port memory cell | Robert A. Ross, Mithkal M. Smadi | 1999-09-21 |
| 5953745 | Redundant memory array | Terry Lee Leasure, Gus Yeung | 1999-09-14 |
| 5907508 | Method and apparatus for single clocked, non-overlapping access in a multi-port memory cell | Robert A. Ross, Mithkal M. Smadi | 1999-05-25 |
| 5896399 | System and method for testing self-timed memory arrays | Michael Kevin Ciraula, Dieter Wendel, Manoj Kumar, Friedrich-Christian Wernicke | 1999-04-20 |
| 5892372 | Creating inversions in ripple domino logic | Michael Kevin Ciraula, Robert P. Masleid, Donald George Mikan, Jr. | 1999-04-06 |
| 5892725 | Memory in a data processing system having uneven cell grouping on bitlines and method therefor | Younes Lotfi, Robert A. Ross, Gus Yeung | 1999-04-06 |
| 5892704 | Wordline amplifier | Robert A. Ross, Gus Yeung | 1999-04-06 |
| 5877976 | Memory system having a vertical bitline topology and method therefor | Robert A. Ross | 1999-03-02 |
| 5870349 | Data processing system and method for generating memory control signals with clock skew tolerance | Robert A. Ross, Mithkal M. Smadi | 1999-02-09 |
| 5831896 | Memory cell | Terry Lee Leasure, Gus Yeung | 1998-11-03 |
| 5812418 | Cache sub-array method and apparatus for use in microprocessor integrated circuits | Robert P. Masleid, John Stephen Muhich | 1998-09-22 |
| 5706237 | Self-restore circuit with soft error protection for dynamic logic circuits | Michael Kevin Ciraula, Terry Lee Leasure, Gus Yeung | 1998-01-06 |
| 5694362 | Method and apparatus for high speed comparison | Kevin X. Zhang, Terry Lee Leasure | 1997-12-02 |