Issued Patents All Time
Showing 51–75 of 76 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7737502 | Raised STI process for multiple gate ox and sidewall protection on strained Si/SGOI sructure with elevated source/drain | Jochen Beintner, Gary B. Bronner, Ramachandra Divakaruni | 2010-06-15 |
| 7730794 | Method for classifying passengers | Jae Ho Hwang | 2010-06-08 |
| 7696573 | Multiple crystallographic orientation semiconductor structures | Shreesh Narasimha, Paul D. Agnello, Xiaomeng Chen, Judson R. Holt, Mukesh V. Khare +1 more | 2010-04-13 |
| 7601646 | Top-oxide-early process and array top oxide planarization | Deok-kee Kim, Ramachandra Divakaruni, Hiroyuki Akatsu, George Worth, Jay William Strane | 2009-10-13 |
| 7595232 | CMOS devices incorporating hybrid orientation technology (HOT) with embedded connectors | Xiaomeng Chen, Yoichi Otani | 2009-09-29 |
| 7592245 | Poly filled substrate contact on SOI structure | David M. Dobuzinsky, Effendi Leobandung, Munir D. Naeem, Brian L. Tessier | 2009-09-22 |
| 7494918 | Semiconductor structures including multiple crystallographic orientations and methods for fabrication thereof | Xiaomeng Chen, Judson R. Holt, Christopher D. Sheraw, Linda Black, Igor Peidous | 2009-02-24 |
| 7491623 | Method of making a semiconductor structure | Xiaomeng Chen, Shwu-Jen Jeng, Hasan M. Nayfeh | 2009-02-17 |
| 7393738 | Subground rule STI fill for hot structure | Munir D. Naeem, Frank D. Tamweber, Xiaomeng Chen | 2008-07-01 |
| 7358172 | Poly filled substrate contact on SOI structure | David M. Dobuzinsky, Effendi Leobandung, Munir D. Naeem, Brian L. Tessier | 2008-04-15 |
| 7037794 | Raised STI process for multiple gate ox and sidewall protection on strained Si/SGOI structure with elevated source/drain | Jochen Beintner, Gary B. Bronner, Ramachandra Divakaruni | 2006-05-02 |
| 6960514 | Pitcher-shaped active area for field effect transistor and method of forming same | Jochen Beintner, Rama Divakaruni, Johnathan E. Faltermeier, Philip L. Flaitz, Oleg Gluschenkov +5 more | 2005-11-01 |
| 6893938 | STI formation for vertical and planar transistors | Munir D. Naeem, Hiroyuki Akatsu, Rolf Weis, David Mark Dobuzinksy, Johnathan E. Faltermeier | 2005-05-17 |
| 6746933 | Pitcher-shaped active area for field effect transistor and method of forming same | Jochen Beintner, Rama Divakaruni, Johnathan E. Faltermeier, Philip L. Flaitz, Oleg Gluschenkov +5 more | 2004-06-08 |
| 6727141 | DRAM having offset vertical transistors and method | Gary B. Bronner, Ramachandra Divakaruni, Jack A. Mandelman | 2004-04-27 |
| 6656817 | Method of filling isolation trenches in a substrate | Ramachandra Divakaruni, Laertis Economikos | 2003-12-02 |
| 6440794 | Method for forming an array of DRAM cells by employing a self-aligned adjacent node isolation technique | — | 2002-08-27 |
| 6404000 | Pedestal collar structure for higher charge retention time in trench-type DRAM cells | Rama Divakaruni, Rajarao Jammy, Jack A. Mandelman, Akira Sudo, Dirk Tobben | 2002-06-11 |
| 6373086 | Notched collar isolation for suppression of vertical parasitic MOSFET and the method of preparing the same | Jack A. Mandelman, Rama Divakaruni | 2002-04-16 |
| 6284666 | Method of reducing RIE lag for deep trench silicon etching | Munir D. Naeem, Gangadhara S. Mathad, Stephan Kudelka, Brian Lee, Heon Lee +3 more | 2001-09-04 |
| 6285725 | Charge pump circuit | Jun Bae Sung | 2001-09-04 |
| 6184107 | Capacitor trench-top dielectric for self-aligned device isolation | Rama Divakaruni, Ulrike Gruening, Jack A. Mandelman, Larry Nesbit, Carl Radens | 2001-02-06 |
| 6143599 | Method for manufacturing memory cell with trench capacitor | Carl Radens, Jochen Beintner | 2000-11-07 |
| 5372950 | Method for forming isolation regions in a semiconductor memory device | Yun-Gi Kim, Cheon-su Bhan | 1994-12-13 |
| 5360753 | Manufacturing method for a semiconductor isolation region | Tai-seo Park, Yun-Gi Kim, Dong Chul Park, Sung Tae Ahn | 1994-11-01 |