Issued Patents All Time
Showing 51–75 of 76 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9104464 | Main processor support of tasks performed in memory | Thomas W. Fox, Hans M. Jacobson, Ravi Nair | 2015-08-11 |
| 9104465 | Main processor support of tasks performed in memory | Thomas W. Fox, Hans M. Jacobson, Ravi Nair | 2015-08-11 |
| 9104532 | Sequential location accesses in an active memory device | Thomas W. Fox, Hans M. Jacobson, Ravi Nair | 2015-08-11 |
| 9088279 | Margin improvement for configurable local clock buffer | James D. Warnock | 2015-07-21 |
| 9081501 | Multi-petascale highly efficient parallel supercomputer | Sameh W. Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle +55 more | 2015-07-14 |
| 9003160 | Active buffered memory | Thomas W. Fox, Hans M. Jacobson, James A. Kahle, Jaime Moreno, Ravi Nair | 2015-04-07 |
| 8990620 | Exposed-pipeline processing element with rollback | Thomas W. Fox, Hans M. Jacobson, Ravi Nair | 2015-03-24 |
| 8972782 | Exposed-pipeline processing element with rollback | Thomas W. Fox, Hans M. Jacobson, Ravi Nair, Daniel A. Prener | 2015-03-03 |
| 8656332 | Automated critical area allocation in a physical synthesized hierarchical design | David J. Geiger, Hung C. Ngo, Ruchir Puri, Haoxing Ren | 2014-02-18 |
| 8560924 | Register file soft error recovery | Thomas W. Fox, Charles D. Wait, Adam J. Muff, Alfred T. Watson, III | 2013-10-15 |
| 8188761 | Soft error detection for latches | Michael K. Gschwind | 2012-05-29 |
| 8069195 | Method and system for a wiring-efficient permute unit | Hung C. Ngo, Jun Sawada | 2011-11-29 |
| 7977965 | Soft error detection for latches | Michael K. Gschwind | 2011-07-12 |
| 7865693 | Aligning precision converted vector data using mask indicating offset relative to element boundary corresponding to precision type | Alexandre E. Eichenberger, Michael K. Gschwind | 2011-01-04 |
| 7739323 | Systems, methods and computer program products for providing a combined moduli-9 and 3 residue generator | Daniel Lipetz, Eric M. Schwarz | 2010-06-15 |
| 7730117 | System and method for a floating point unit with feedback prior to normalization and rounding | Juergen Haess, Michael K. Kroener, Martin S. Schmookler, Eric M. Schwarz, Son Dao-Trong | 2010-06-01 |
| 7721171 | Scheme to optimize scan chain ordering in designs | Mark A. Erle, Daniel Lipetz | 2010-05-18 |
| 7660838 | System and method for performing decimal to binary conversion | Steven R. Carlough, Wen H. Li, Eric M. Schwarz | 2010-02-09 |
| 6842765 | Processor design for extended-precision arithmetic | Robert F. Enenkel, Fred Gehrung Gustavson, Jose E. Moreira | 2005-01-11 |
| 6131182 | Method and apparatus for synthesizing and optimizing control logic based on SRCMOS logic array macros | Michael P. Beakes, Barbara Alana Chappell, Terry I. Chappell, Gary S. Ditlow, Barry Lee Dorfman +5 more | 2000-10-10 |
| 6005416 | Compiled self-resetting CMOS logic array macros | Michael P. Beakes, Barbara Alana Chappell, Terry I. Chappell, Gary S. Ditlow, Barry Lee Dorfman +2 more | 1999-12-21 |
| 5751619 | Recurrent adrithmetical computation using carry-save arithmetic | Ramesh Chandra Agarwal, Fred Gehrung Gustavson | 1998-05-12 |
| 5748012 | Methodology to test pulsed logic circuits in pseudo-static mode | Michael P. Beakes, Barbara A. Chappell, Terry I. Chappell, Rudolf A. Haring, Talal K. Jaber +1 more | 1998-05-05 |
| 5633820 | Self-resetting CMOS parallel adder with a bubble pipelined architecture, tri-rail merging logic, and enhanced testability | Michael P. Beakes, Barbara Alana Chappell, Terry I. Chappell, Thao N. Nguyen | 1997-05-27 |
| 5471188 | Fast comparator circuit | Barbara A. Chappell, Terry I. Chappell, Stanley E. Schuster | 1995-11-28 |