Issued Patents All Time
Showing 26–50 of 82 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11830807 | Placing top vias at line ends by selective growth of via mask from line cut dielectric | Ekmini Anuja De Silva, Dominik Metzler, John C. Arnold | 2023-11-28 |
| 11812668 | Pillar-based memory hardmask smoothing and stress reduction | Michael Rizzolo, Theodorus E. Standaert, Dominik Metzler | 2023-11-07 |
| 11778929 | Selective encapsulation for metal electrodes of embedded memory devices | Ekmini Anuja De Silva, Jennifer Church | 2023-10-03 |
| 11751492 | Embedded memory pillar | Dexin Kong, Ekmini Anuja De Silva, Daniel Schmidt | 2023-09-05 |
| 11744083 | Fabrication of embedded memory devices utilizing a self assembled monolayer | Ekmini Anuja De Silva, Chih-Chao Yang | 2023-08-29 |
| 11699592 | Inverse tone pillar printing method using organic planarizing layer pillars | Nelson Felix, Ekmini Anuja De Silva, Praveen Joseph | 2023-07-11 |
| 11681213 | EUV pattern transfer using graded hardmask | Nelson Felix, Luciana Meli Thompson, Ekmini Anuja De Silva | 2023-06-20 |
| 11682558 | Fabrication of back-end-of-line interconnects | Chi-Chun Liu, Nelson Felix, Ekmini Anuja De Silva | 2023-06-20 |
| 11621294 | Embedding MRAM device in advanced interconnects | Saumya Sharma, Tianji Zhou, Chih-Chao Yang | 2023-04-04 |
| 11502242 | Embedded memory devices | Chih-Chao Yang, Michael Rizzolo, Theodorus E. Standaert | 2022-11-15 |
| 11500293 | Patterning material film stack with hard mask layer configured to support selective deposition on patterned resist layer | Ekmini Anuja De Silva, Indira Seshadri, Jing Guo, Nelson Felix | 2022-11-15 |
| 11501969 | Direct extreme ultraviolet lithography on hard mask with reverse tone | Yann Mignot, Yongan Xu, Ekmini Anuja De Silva, Chi-Chun Liu | 2022-11-15 |
| 11495538 | Fully aligned via for interconnect | Ruilong Xie, Christopher J. Waskiewicz, Chih-Chao Yang, Lawrence A. Clevenger | 2022-11-08 |
| 11462583 | Embedding magneto-resistive random-access memory devices between metal levels | Chih-Chao Yang, Daniel C. Edelstein, John C. Arnold, Theodorus E. Standaert | 2022-10-04 |
| 11437083 | Two-bit magnetoresistive random-access memory device architecture | Eric Raymond Evarts | 2022-09-06 |
| 11404317 | Method for fabricating a semiconductor device including self-aligned top via formation at line ends | John C. Arnold, Dominik Metzler, Ekmini Anuja De Silva | 2022-08-02 |
| 11373880 | Creating different width lines and spaces in a metal layer | Christopher J. Penny, Ekmini Anuja De Silva, Abraham Arceo de la Pena | 2022-06-28 |
| 11361987 | Forming decoupled interconnects | Saumya Sharma, Tianji Zhou, Chih-Chao Yang | 2022-06-14 |
| 11355442 | Forming self-aligned multi-metal interconnects | Ekmini Anuja De Silva | 2022-06-07 |
| 11302573 | Semiconductor structure with fully aligned vias | Ekmini Anuja De Silva, Praveen Joseph, Nelson Felix | 2022-04-12 |
| 11302639 | Footing flare pedestal structure | Chih-Chao Yang, Baozhen Li | 2022-04-12 |
| 11276607 | Selective patterning of vias with hardmasks | John C. Arnold, Dominik Metzler, Timothy Mathew Philip, Sagarika Mukesh | 2022-03-15 |
| 11251368 | Interconnect structures with selective capping layer | Tianji Zhou, Saumya Sharma, Chih-Chao Yang | 2022-02-15 |
| 11239160 | E-fuse with dielectric zipping | Tianji Zhou, Saumya Sharma, Chih-Chao Yang | 2022-02-01 |
| 11227997 | Planar resistive random-access memory (RRAM) device with a shared top electrode | Saumya Sharma, Tianji Zhou, Chih-Chao Yang | 2022-01-18 |