Issued Patents All Time
Showing 376–400 of 1,279 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10692722 | Single process for linear and metal fill | Praneet Adusumilli, Oscar van der Straten, Chih-Chao Yang | 2020-06-23 |
| 10680085 | Transistor structure with varied gate cross-sectional area | Dominic J. Schepis, Pranita Kerber, Qiqing C. Ouyang | 2020-06-09 |
| 10679890 | Nanosheet structure with isolated gate | Xin Miao, Joshua M. Rubin | 2020-06-09 |
| 10672865 | Deformable and flexible capacitor | Karthik Balakrishnan, Stephen W. Bedell, Pouya Hashemi | 2020-06-02 |
| 10672862 | High density vertically integrated FEOL MIM capacitor | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2020-06-02 |
| 10672490 | One-time-programmable memory in a high-density three-dimensional structure | Bahman Hekmatshoartabari | 2020-06-02 |
| 10665541 | Biconvex low resistance metal wire | Praneet Adusumilli, Oscar van der Straten | 2020-05-26 |
| 10658513 | Formation of FinFET junction | Kevin K. Chan, Pouya Hashemi, Ali Khakifirooz, John A. Ott | 2020-05-19 |
| 10658507 | Vertical transistor pass gate device | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2020-05-19 |
| 10658494 | Transistors and methods of forming transistors using vertical nanowires | Dominic J. Schepis | 2020-05-19 |
| 10658462 | Vertically stacked dual channel nanosheet devices | Choonghyun Lee, Jingyun Zhang, Pouya Hashemi, Takashi Ando | 2020-05-19 |
| 10658429 | High-density field-enhanced ReRAM integrated with vertical transistors | Takashi Ando, Pouya Hashemi | 2020-05-19 |
| 10658353 | Stacked electrostatic discharge diode structures | Bahman Hekmatshoartabari, Karthik Balakrishnan, Tak H. Ning | 2020-05-19 |
| 10651308 | Self aligned top extension formation for vertical transistors | Oleg Gluschenkov, Sanjay C. Mehta, Shogo Mochizuki | 2020-05-12 |
| 10651295 | Forming a fin using double trench epitaxy | Veeraraghavan S. Basker, Pouya Hashemi, Shogo Mochizuki | 2020-05-12 |
| 10651123 | High density antifuse co-integrated with vertical FET | Pouya Hashemi, Miaomiao Wang, Takashi Ando | 2020-05-12 |
| 10651089 | Low thermal budget top source and drain region formation for vertical transistors | Shogo Mochizuki, Oleg Gluschenkov | 2020-05-12 |
| 10651042 | Salicide bottom contacts | Praneet Adusumilli, Oscar van der Straten | 2020-05-12 |
| 10644109 | Digital alloy vertical lamellae FinFET with current flow in alloy layer direction | Karthik Balakrishnan, Stephen W. Bedell, Pouya Hashemi, Bahman Hekmatshoartabari | 2020-05-05 |
| 10644007 | Decoupling capacitor on strain relaxation buffer layer | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2020-05-05 |
| 10643907 | Structure and method for tensile and compressive strained silicon germanium with same germanium concentration by single epitaxy step | Pranita Kerber, Qiqing C. Ouyang, Dominic J. Schepis | 2020-05-05 |
| 10636804 | Stacked FinFET programmable inverter (EPROM) | Karthik Balakrishnan, Tak H. Ning, Bahman Hekmatshoartabari | 2020-04-28 |
| 10629730 | Body contact in Fin field effect transistor design | Tak H. Ning, Jeng-Bang Yau, Bahman Hekmatshoartabari | 2020-04-21 |
| 10622486 | Tilted nanowire transistor | Pouya Hashemi, Kangguo Cheng, Karthik Balakrishnan | 2020-04-14 |
| 10622406 | Dual metal nitride landing pad for MRAM devices | Oscar van der Straten, Michael Rizzolo | 2020-04-14 |